參數(shù)資料
型號(hào)： M29F105B
廠商： 意法半導(dǎo)體
英文描述： 1Mbit (64Kb x16, Block Erase) Single Supply Flash Memory(1Mb閃速存儲(chǔ)器)
中文描述： 為1Mbit（64Kb的x16插槽，塊擦除）單電源閃存存儲(chǔ)器（1MB閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 4/28頁(yè)
文件大小： 200K
代理商： M29F105B
Instructions
TeninstructionsaredefinedtoperformReadArray,
Auto Select (to read the Electronic Signature or
Block Protection Status), Program, Block Protect,
Blocks Unprotect,BlockErase, Chip Erase, Erase
Suspendand Erase Resume. The internal P/E.C.
automaticallyhandles all timing and verification of
the Program and Erase operations. The Status
RegisterDataPolling,ToggleandErrorbitsmaybe
read at any time, duringprogramming or erase,to
monitor the progressof the operation.
Instructionsare composedof upto six cycles. The
first two cycles input a Coded sequence to the
CommandInterfacewhich iscommontoall instruc-
tions (see Table 9). The third cycle inputs the
instruction set-up command. Subsequent cycles
outputtheaddresseddata,ElectronicSignatureor
Block Protection Status for Read operations. In
orderto giveadditionaldataprotection,the instruc-
tionsfor Programand Blockor Chip Erase require
furthercommandinputs.ForaPrograminstruction,
the fourth command cycle inputs the addressand
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
furtherCodedsequencebeforethecommandcon-
firmation on the sixth cycle. Erasure of a memory
blockmaybesuspended,inorderto readdatafrom
anotherblock or to programdata in anotherblock,
and then resumed.
The Block Protect and Blocks Unprotect com-
mands allow these operations to be performed in
theapplication.They providea sixcycle command
access of the equivalent bus operations. This en-
ables updates of the memory protected blocks in
the field, without the use of a programmer or the
need to generate 12V on the application.
When power is first applied or if V
CC
falls below
V
LKO
, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table1.
Address Inputs (A0-A15)
. The addressinputsfor
thememoryarrayarelatchedduringa writeopera-
tion on the falling edge of Chip Enable E or Write
EnableW. WhenA9 is raisedto V
ID
, eithera Read
ElectronicSignatureManufacturerorDeviceCode,
BlockProtectionStatusora WriteBlockProtection
or BlockUnprotectionisenableddependingon the
combinationof levelson A0,A1 A6,A12 and A15.
Data Input/Outputs (DQ0-DQ15).
The input is
data to be programmedin the memory array or a
commandto be writtento the C.I.Bothare latched
ontherisingedgeof ChipEnableEorWrite Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
registerData Polling bitDQ7, the ToggleBits DQ6
and DQ2, the Error bit DQ5or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsare disabled and when RPNC is at a Low
level.
Chip Enable (E).
The Chip Enable input activates
the memory control logic, input buffers, decoders
andsenseamplifiers.EHighdeselectsthememory
andreducesthepowerconsumptiontothestandby
level. E can also be used to control writing to the
command register and to the memory array, while
Wremainsat alowlevel.TheChipEnablemustbe
forced to V
ID
duringthe Block Unprotectionopera-
tion.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
ID
level during
BlockProtectionand Unprotectionoperations.
WriteEnable(W).
Thisinputcontrolswritingto the
CommandRegisterand Addressand Datalatches.
V
CC
Supply Voltage.
The power supply for all
operations(Read, Program and Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
DEVICEOPERATIONS
SeeTables 4, 5 and6.
Read.
Read operations are used to output the
contentsof the Memory Array, the ElectronicSig-
nature,the StatusRegister or the BlockProtection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Write.
Writeoperationsareusedto giveInstruction
Commands to the memoryor to latch input datato
beprogrammed.Awrite operationis initiatedwhen
Chip Enable E is Low and Write Enable W is Low
withOutput EnableG High.Addressesarelatched
onthefallingedge of Wor Ewhicheveroccurs last.
CommandsandInputDataarelatchedon therising
edge of W or E whichever occurs first.
OutputDisable.
Thedata outputsarehighimped-
ancewhen the OutputEnable G is Highwith Write
EnableW High.
Standby.
The memory is in standby when Chip
EnableE is Highand the P/E.C.is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or Write EnableW inputs.
4/28
M29F105B
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