參數(shù)資料
型號： M29F100-T70M3TR
廠商： 意法半導(dǎo)體
元件分類： FLASH
英文描述： 1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory
中文描述： 1兆位的128KBx8或64Kbx16，有啟動區(qū)域的單電源閃存
文件頁數(shù)： 4/30頁
文件大?。?/td> 207K
代理商： M29F100-T70M3TR
AI01275B
3V
High Speed
0V
1.5V
2.4V
Standard
0.45V
2.0V
0.8V
Figure 4. AC Testing Input Output Waveform
AI01276B
1.3V
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 5. AC Testing Load Circuit
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
VIN =0V
6
pF
COUT
Output Capacitance
VOUT =0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 12. Capacitance(1) (TA =25
°C, f = 1 MHz )
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAAh
in the Byte-wide configuration or address 5555h in
the Word-wide configuration on third cycle after the
two Coded cycles. The Block Erase Confirm com-
mand 30h is similarly written on the sixth cycle after
another two Coded cycles. During the input of the
second command an addresswithin the block to be
erased is given and latched into the memory. Addi-
tional block Erase Confirm commands and block
addresses can be written subsequently to erase
other blocks in parallel, without further Coded cy-
cles. The erase will start after the erase timeout
period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for
other blocks must be given within this delay. The
input of a new Erase Confirm command will restart
the timeout period. The status of the internal timer
can be monitored through the level of DQ3, if DQ3
is ’0’ the Block Erase Command has been given
and the timeout is running, if DQ3 is ’1’, the timeout
has expired and the P/E.C. is erasing the Block(s).
If the second command given is not an erase
confirm or if the Coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Array. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
to erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register
status bits.
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
Input Pulse Voltages
0 to 3V
0.45V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Table 11. AC Measurement Conditions
12/30
M29F100T, M29F100B
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