參數(shù)資料
型號： M295V400T-55N6R
廠商： 意法半導(dǎo)體
英文描述： 4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory
中文描述： 4兆位512KB的x8或256Kb的x16插槽，啟動座單電源閃存
文件頁數(shù)： 6/34頁
文件大?。?/td> 231K
代理商： M295V400T-55N6R
SIGNALDESCRIPTIONS
See Figure 1 and Table1.
AddressInputs (A0-A17)
. The addressinputs for
thememoryarrayare latchedduringa writeopera-
tion on the falling edge of Chip Enable E or Write
Enable W. In Word-wide organisation the address
lines are A0-A17, in Byte-wide organisation
DQ15A–1 acts as an additional LSB address line.
WhenA9 is raisedto V
ID
, either a Read Electronic
Signature Manufacturer or Device Code, Block
Protection Status or a Write Block Protection or
Block Unprotection is enabled depending on the
combination of levels on A0, A1,A6, A12and A15.
Data Input/Outputs (DQ0-DQ7).
These In-
puts/Outputs are used in theByte-wide and Word-
wide organisations. The input is data to be
programmed in the memory array or a command
to be written to the C.I. Both are latched on the
rising edge of Chip Enable E or Write Enable W.
The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the EraseTimer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsare disabledandwhenRP isata Lowlevel.
Data Input/Outputs (DQ8-DQ14 and DQ15A–1).
These Inputs/Outputs are additionally used in the
Word-wideorganisation.When BYTEis HighDQ8-
DQ14 and DQ15A–1 act as the MSB of the Data
Input or Output, functioning as described for DQ0-
DQ7 above, and DQ8-DQ15 are ’don’t care’ for
command inputs or status outputs. When BYTEis
Low,DQ8-DQ14are highimpedance, DQ15A–1 is
the Address A–1input.
Chip Enable (E).
The Chip Enable input activates
the memory control logic, input buffers, decoders
andsenseamplifiers. EHighdeselectsthememory
andreducesthe powerconsumption to thestandby
level. E can also be used to control writing to the
command register and to the memoryarray, while
Wremainsat a lowlevel.The ChipEnablemustbe
forcedto V
ID
duringthe BlockUnprotection opera-
tion.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
ID
level during
BlockProtection and Unprotection operations.
WriteEnable(W).
Thisinput controlswritingtothe
CommandRegisterandAddressand Datalatches.
Byte/Word Organization Select (BYTE).
The
BYTEinput selectsthe outputconfiguration for the
device: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTEis Low, the Byte-wide mode is
selectedand the data is read and programmed on
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is se-
lected and the data is read and programmed on
DQ0-DQ15.
Ready/Busy Output (RB).
Ready/Busy is an
open-drainoutputandgivestheinternalstateofthe
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructions except the Erase Suspendinstruction.
WhenRB isHigh,thedevice is readyfor anyRead,
Program or Erase operation. The RB will also be
High when the memoryis put in EraseSuspendor
Standbymodes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling RP to
V
IL
for at least 500ns. When the reset pulse is
given,if thememoryis in Reador Standbymodes,
it willbe available for new operations in 50ns after
the rising edge of RP. If the memory is in Erase,
Erase Suspend or Program modes the reset will
take 10
μ
s during which the RB signal will be held
atV
IL
.Theendofthememoryresetwillbeindicated
by the rising edge of RB. A hardware reset during
anEraseor Program operationwillcorruptthedata
being programmed or the sector(s) being erased.
Temporary block unprotection is made by holding
RP at V
ID
. In this condition previously protected
blocks can be programmed or erased.The transi-
tion of RPfrom V
IH
to V
ID
must slower than 500ns.
When RP is returned from V
ID
to V
IH
all blocks
temporarily unprotected will be again protected.
V
CC
Supply Voltage.
The power supply for all
operations (Read, Program and Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
6/34
M29F400T, M29F400B
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