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參數(shù)資料
| 型號： | M13S64164A-6TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| 中文描述： | 4M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66 |
| 文件頁數(shù)： | 9/49頁 |
| 文件大小： | 1526K |
| 代理商： | M13S64164A-6TG |
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ES MT
Preliminary
M13S64164A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 0.3 9/49
Command Truth Table
COMMAND
CKEn-1 CKEn
CS
RAS
CAS
WE
DM
BA0,1
A10/AP
A11,
A9~A0
Note
Register
Register
Extended MRS
Mode Register Set
H
H
X
X
L
L
L
L
L
L
L
L
X
X
OP CODE
OP CODE
1,2
1,2
3
Auto Refresh
H
Entry
H
L
L
L
L
H
X
X
3
L
H
H
H
3
Refresh
Self
Refresh
Exit
L
H
H
X
X
X
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Row Address
Auto Precharge Disable
L
4
Read &
Column
Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
H
Column
Address
4
Auto Precharge Disable
L
4
Write &
Column
Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
H
Column
Address
4,6
Burst Stop
Bank Selection
All Banks
H
X
L
H
H
L
X
X
L
H
7
5
8
V
X
Precharge
H
X
L
L
H
L
X
X
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Active Power Down
Exit
L
H
X
X
Entry
H
L
X
Precharge Power Down
Mode
Exit
L
H
X
X
DM
H
V
X
H
L
X
H
X
H
No Operation Command
H
X
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 1 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1 : Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
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