參數(shù)資料
型號(hào)： M13S64164A-6TG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
中文描述： 4M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66
文件頁(yè)數(shù)： 31/49頁(yè)
文件大?。?/td> 1526K
代理商： M13S64164A-6TG
ES MT
Preliminary
M13S64164A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 0.3 31/49
Current State
CS
RAS CAS
WE
Address
Command
Action
H
X
X
X
X
DESEL
NOP (Idle after t
RP
)
L
H
H
H
X
NOP
NOP (Idle after t
RP
)
L
H
H
L
BA
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
RE-FRESHING
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after t
RP
)
L
H
H
H
X
NOP
NOP (Idle after t
RP
)
L
H
H
L
BA
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
MODE
REGISTER
SETTING
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL of any bank is not idle.
6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be
performed.
7. Refer to “Read with Auto Precharge: for more detailed information.
ILLEGAL = Device operation and / or data integrity are not guaranteed.
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