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| 型號： | M12L128168A-6TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, TSOP2-54 |
| 文件頁數(shù)： | 7/43頁 |
| 文件大?。?/td> | 804K |
| 代理商： | M12L128168A-6TG |
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ESMT
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
7/43
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1
CKEn
CS RAS
CAS
WE
DQM
A13
A12
A10/AP
A11
A9~A0
Note
Register
Mode Register set
Auto Refresh
H
X
H
L
L
L
L
L
X
OP CODE
1,2
3
3
3
3
Entry
H
L
L
L
H
X
X
L
H
L
H
X
L
H
X
H
H
X
H
X
X
X
Refresh
Self
Refresh
Exit
L
H
X
Bank Active & Row Addr.
H
X
V
Row Address
Auto Precharge Disable
L
4
Read &
Column Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
H
Column
Address
(A0~A8)
Column
Address
(A0~A8)
4,5
Auto Precharge Disable
L
4
Write &
Column Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
H
4,5
Burst Stop
H
X
L
H
H
L
X
X
6
Bank Selection
V
L
Precharge
All Banks
H
X
L
L
H
L
X
X
H
X
H
X
X
X
Entry
H
L
L
V
V
V
X
Clock Suspend or
Active Power Down
Exit
L
H
X
X
X
X
X
X
H
X
X
X
Entry
H
L
L
H
H
H
X
H
X
X
X
Precharge Power Down Mode
Exit
L
H
L
V
V
V
X
X
DQM
H
X
V
X
7
H
X
X
X
No Operating Command
H
X
L
H
H
H
X
X
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note : 1.OP Code : Operating Code
A0~A11 & A13~A12 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.A13~A12 : Bank select addresses.
If A13 and A12 are “Low” at read ,write , row active and precharge ,bank A is selected.
If A13 is “Low” and A12 is “High” at read ,write , row active and precharge ,bank B is selected.
If A13 is “High” and A12 is “Low” at read ,write , row active and precharge ,bank C is selected.
If A13 and A12 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , A13 and A12 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
相關(guān)PDF資料 |
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| M12L128168A-7TG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L128168A-6TG2L | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:ABSOLUTE MAXIMUM RATINGS |
| M12L128168A-6TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L128168A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L128168A-7BG2L | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:ABSOLUTE MAXIMUM RATINGS |
| M12L128168A-7BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
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