參數(shù)資料
型號: M12L128168A-6TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 5/43頁
文件大小: 804K
代理商: M12L128168A-6TG
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V
,
T
A
= 0 to 70 C
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
5/43
)
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
-5
-6
-7
Unit
Note
Row active to row active delay
t
RRD(min)
10
12
14
ns
1
RAS to CAS delay
Row precharge time
t
RCD(min)
15
18
20
ns
1
t
RP(min)
15
18
20
ns
1
t
RAS(min)
38
40
42
ns
1
Row active time
t
RAS(max)
100
us
@ Operating
t
RC(min)
53
58
63
ns
1
Row cycle time
@ Auto refresh t
RFC(min)
55
60
70
ns
1,5
Last data in to col. address delay
t
CDL(min)
1
t
CK
2
Last data in to row precharge
t
RDL(min)
2
t
CK
2
Last data in to burst stop
t
BDL(min)
1
t
CK
2
Refresh period (4,096 rows)
t
BEF(max)
64
ms
6
Output
870
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
50pF
Z0 =50
50pF
50
Vtt = 1.4V
3.3V
1200
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