參數(shù)資料
型號(hào)： LXT971ABE
英文描述： LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC
中文描述： 網(wǎng)絡(luò)收發(fā)器|單|的CMOS | BGA封裝| 64管腳|塑料
文件頁數(shù)： 50/68頁
文件大?。?/td> 1177K
代理商： LXT971ABE
LXT9784
—
Low-Power Octal PHY
50
Datasheet
Data and control bits are transmitted and received serially synchronous to MCLK, in ten bit
segments delimited by a pulse on SYNC, on RXD
n
and TXD
n
respectively.
3.4.1
SMII Clock
In SMII mode of operation, the master input clock (MCLK) frequency should be 125 MHz, ±
50ppm, with a duty-cycle between 35% and 65% inclusive.
Figure 14. Typical SMII Application
LXT9784
P0_MDI
P1_MDI
P2_MDI
P3_MDI
P4_MDI
P5_MDI
P6_MDI
P7_MDI
MDI Ports
RBIAS100_0
RBIAS10_0
Analog pins
LED0_[A:C]
LED1_[A:C]
LED2_[A:C]
LED3_[A:C]
LED4_[A:C]
LED5_[A:C]
LED6_[A:C]
LED7_[A:C]
Per Port
LEDs
MODE[2:0]
RESET
MCLK
FRC34
Configuration
MDIO
MDC
MII Management
Interface
ID[1:0]
PHY ID
SMII0_[1:0]
SMII1_[1:0]
SMII2_[1:0]
SMII3_[1:0]
SMII4_[1:0]
SMII5_[1:0]
SMII6_[1:0]
SMII7_[1:0]
SMII
Interfaces
RXD
TXD
TPIP
INT
Interrupt
RBIAS100_1
RBIAS10_1
SCRMBP
MDIX
BP4B5B
FRCLNK
SYNC
TCK
TI
TEXEC
TOUT
Test Port
TPIN
TPOP
TPON
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