- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369886 > LXT971ABE LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC PDF資料下載
參數(shù)資料
| 型號(hào)： | LXT971ABE |
| 英文描述： | LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器|單|的CMOS | BGA封裝| 64管腳|塑料 |
| 文件頁(yè)數(shù)： | 40/68頁(yè) |
| 文件大小： | 1177K |
| 代理商： | LXT971ABE |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)當(dāng)前第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
LXT9784
—
Low-Power Octal PHY
40
Datasheet
2.6
Hardware Control Interface
The LXT9784 can be configured for unmanaged applications, using external pins (hardware
control) as described in the following paragraphs.
2.6.1
MDI-X
(MDI Crossover)
During RESET, enables the auto-switch feature. If this feature was disabled, then after reset the
MDI-X pin controls the manual MDI/MDI-X switching.
When MDI-X = 1, the MDI port is forced to MDI-X
(cross- over mode).
When MDI-X = 0, the MDI port is forced to MDI
(straight-through mode).
2.6.2
FRCLNK
(Force Link)
During RESET:
When FRCLNK = 1, it
forces good link
(PHY reg17, bit 11),
link integrity
(PHY reg17, bit 1),
and
disables auto-negotiation
(PHY reg0, bit 12)
When FRCLNK = 0, Normal Operation.
If FRCLNK was set, then after reset the FRCLNK pin will control speed selection (PHY reg0, bit
13), where:
When FRCLNK = 1, it forces 100 Mbps.
When FRCLNK = 0, it forces 10 Mbps.
The FRCLNK pin and bit 11 in PHY register 11
’
h are ORed together.
2.6.3
FRC34
(Force 34 Transmit Pattern)
The FRC34 pin and bit 12 in PHY register 11
’
h are ORed together.
2.6.4
BP4B5B
(4B/5B Bypass)
To enter 4B/5B bypass mode, this pin must be set high after the end of reset. During reset, this pin
must be pulled down to ensure proper operation of the LXT9784.
5
Not used
6
TDN
_n
7
Not used
8
Not used
Table 15. Crossed-over Pin Assignments
Contact
MDI Signal
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT971ALC | LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC |
| LXT971ALE | LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC |
| LXT974QC | LAN Transceiver |
| LXT975QC | LAN Transceiver |
| LXT9761 | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971ALC | 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971ALE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971LC | 制造商:Intel 功能描述: |
| LXT972A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。