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參數(shù)資料
| 型號： | LXT6234 |
| 廠商： | Intel Corp. |
| 英文描述： | E-Rate Multiplexer |
| 中文描述： | 電子速率復(fù)用器 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | LXT6234 |
LXT6234
—
E-Rate Multiplexer
8
Datasheet
36
MNAT
National Bit Input.
National Bit input that is placed in the 12th bit of the frame as per ITU G.742, G.751
specifications.
37
MAIS
AIS/Error Bit Input.
AIS Bit input that is placed in the 11th bit of the frame, as per ITU G.742, G.751
specifications.
41
MHMUXC
High speed Multiplexer Clock Input.
Clock input for Multiplexer functions and NRZ high speed data
output. For standard rate applications, this clock must have a frequency of ±30 ppm for the 8448 kbit/s
operation and ±20 ppm for the 34368 kbit/s operation as per ITU G.703.
44
MHNRZI
HDB3 Encoder #5 NRZ Input.
HDB3 Encoder #5 (High speed) NRZ input clocked on the rising edge
of MHHDB3C.
45
MHHDB3C
HDB3 Encoder #5 Clock Input.
When used in conjunction with the Multiplexer, this pin should be tied
to the high speed Multiplexer Clock, MHMUXC, P41.
48
DHDPI
HDB3 Decoder #5 Positive Data Input.
HDB3 Decoder #5 (High Speed) positive rail input clocked on
the rising edge of DHHDB3C.
49
DHDNI
HDB3 Decoder #5 Negative Data Input.
HDB3 Decoder #5 (High Speed) positive rail input clocked on
the rising edge of DHHDB3C.
50
DHHDB3C
HDB3 Decoder #5 Clock Input.
When used in conjunction with the Demultiplexer, this pin should be
tied to the high speed Demultiplexer Clock, DHMUXC, P57.
56
DHNRZI
Demultiplexer NRZ Data Input.
Demultiplexer NRZ input clocked on rising edge of DHDMXC.
57
DHDMXC
High speed Demultiplexer Clock Input.
Clock input for Demultiplexer functions and NRZ high speed
data in. For standard rate applications, this clock must have a frequency of ±30 ppm for the 8448 kbit/s
operation and ±20 ppm for the 34368 kbit/s operation as per ITU G.703.
82
DLNRZI1
HDB3 Encoder #1 NRZ Data Input.
HDB3 Encoder #1 NRZ input clocked on rising edge of DLCI1.
86
DLNRZI2
HDB3 Encoder #2 NRZ Data Input.
HDB3 Encoder #2 NRZ input clocked on rising edge of DLCI2.
92
DLNRZI3
HDB3 Encoder #3 NRZ Data Input.
HDB3 Encoder #3 NRZ input clocked on rising edge of DLCI3.
96
DLNRZI4
HDB3 Encoder #4 NRZ Data Input.
HDB3 Encoder #4 NRZ input clocked on rising edge of DLCI4.
83
DLCI1
HDB3 Encoder #1 Clock Input.
Clock input for HDB3 Encoder #1.
87
DLCI2
HDB3 Encoder #2 Clock Input.
Clock input for HDB3 Encoder #2.
93
DLCI3
HDB3 Encoder #3 Clock Input.
Clock input for HDB3 Encoder #3.
97
DLCI4
HDB3 Encoder #4 Clock Input.
Clock input for HDB3 Encoder #4.
54
MODE
E12/E23 Mode Select.
Mode selection for multiplexer/demultiplexer operation. A low signal selects
4E1/E2 multiplexing. A high signal selects 4E2/E3 multiplexing.
100
LREFCK
Tributary Reference Clock.
This clock is used as a reference for the Force AIS functions (See Pin 6
Description). For standard rate applications, this clock must have a frequency of ±50 ppm for the 2048
kbit/s operation and ±30 ppm for the 8448 kbit/s operation as per ITU G.703.
60
CE
Chip Enable.
A high signal forces all outputs into tri-state; used for PCB Testing. This signal should be
low for normal operation.
63
RSTN
Reset.
An active low reset pin. Must be pulsed low on power up to initialize all internal circuits after
V
CC
and clocks are stable.
15, 40
65, 90
GND
Ground.
Ground Reference.
16, 39
64, 91
V
CC
Voltage.
5-volt supply voltage.
Table 1. Input Signals (Continued)
Pin #
Sym
Description
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