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參數(shù)資料
| 型號： | LXT6234 |
| 廠商： | Intel Corp. |
| 英文描述： | E-Rate Multiplexer |
| 中文描述： | 電子速率復用器 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | LXT6234 |
E-Rate Multiplexer
—
LXT6234
Datasheet
7
Table 1. Input Signals
Pin #
Sym
Description
1
MLDPI1
HDB3 Decoder #1 Positive Data Input. HDB3 Decoder #1 positive rail input clocked on the positive
transitions of the clock signal MLCK1.
2
MLDNI1
HDB3 Decoder #1 Negative Data Input. HDB3 Decoder #1 negative rail input clocked on the positive
transitions of the clock signal MLCK1.
8
MLDPI2
HDB3 Decoder #2 Positive Data Input. HDB3 Decoder #2 positive rail input clocked on the positive
transitions of the clock signal MLCK2.
9
MLDNI2
HDB3 Decoder #2 Negative Data Input. HDB3 Decoder #2 negative rail input clocked on the positive
transitions of the clock signal MLCK2.
17
MLDPI3
HDB3 Decoder #3 Positive Data Input.
HDB3 Decoder #3 positive rail input clocked on the positive
transitions of the clock signal MLCK3.
18
MLDNI3
HDB3 Decoder #3 Negative Data Input.
HDB3 Decoder #3 negative rail input clocked on the positive
transitions of the clock signal MLCK3.
24
MLDPI4
HDB3 Decoder #4 Positive Data Input.
HDB3 Decoder #4 positive rail input clocked on the positive
transitions of the clock signal MLCK4.
25
MLDNI4
HDB3 Decoder #4 Negative Data Input.
HDB3 Decoder #4 negative rail input clocked on the positive
transitions of the clock signal MLCK4.
7
MLCK1
Multiplexer Tributary #1 Clock Input.
Clock input for Multiplexer side tributary channel #1. This clock
is used by both the associated HDB3 decoder and the Multiplexer. For standard rate applications, this
clock must have a frequency of ±50 ppm for 2048 kbit/s operation and ±30 ppm for the 8448 kbit/s
operation as per ITU G.703.
14
MLCK2
Multiplexer Tributary #2 Clock Input.
Idem as MLCK1 with tributary #2 in.
23
MLCK3
Multiplexer Tributary #3 Clock Input.
Idem as MLCK1 with tributary #3 in.
30
MLCK4
Multiplexer Tributary #4 Clock Input.
Idem as MLCK1 with tributary #4 in.
5
MLNRZI1
Multiplexer Tributary #1 NRZ Data Input.
Multiplexer tributary NRZ input clocked on the falling edge
of the clock signal MLCK1.
12
MLNRZI2
Multiplexer Tributary #4 NRZ Data Input.
Multiplexer tributary NRZ input clocked on the falling edge
of the clock signal MLCK2.
21
MLNRZI3
Multiplexer Tributary #3 NRZ Data Input.
Multiplexer tributary NRZ input clocked on the falling edge
of the clock signal MLCK3.
28
MLNRZI4
Multiplexer Tributary #4 NRZ Data Input.
Multiplexer tributary NRZ input clocked on the falling edge
of the clock signal MLCK4.
6
MLFAIS1
Force AIS on Multiplexer Tributary #1.
Active high signal to force AIS (all 1
’
s) data and LREFCK
clock on Multiplexer tributary #1.
13
MLFAIS2
Force AIS on Multiplexer Tributary #2.
Active high signal to force AIS (all 1
’
s) data and LREFCK
clock on Multiplexer tributary #2.
22
MLFAIS3
Force AIS on Multiplexer Tributary #3.
Active high signal to force AIS (all 1
’
s) data and LREFCK
clock on Multiplexer tributary #3.
29
MLFAIS4
Force AIS on Multiplexer Tributary #4.
Active high signal to force AIS (all 1
’
s) data and LREFCK
clock on Multiplexer tributary #4.
66
AUXI1
Auxiliary Flag/Data #1 Input.
The signal on this pin is clocked into the frame at the stuffing bit location
(J1) when justification is such that tributary data is NOT placed at this location. A high on alarm signal
MESA1 indicates this condition during the current frame.
75
AUXI2
Auxiliary Flag/Data #2 Input.
See AUXI1 Description. MESA2 is relevant indication signal.
76
AUXI3
Auxiliary Flag/Data #3 Input.
See AUXI1 Description. MESA3 is relevant indication signal.
77
AUXI4
Auxiliary Flag/Data #4 Input.
See AUXI1 Description. MESA4 is relevant indication signal.
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