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參數(shù)資料
| 型號： | LXT6234 |
| 廠商： | Intel Corp. |
| 英文描述： | E-Rate Multiplexer |
| 中文描述： | 電子速率復(fù)用器 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | LXT6234 |
Datasheet
3
E-Rate Multiplexer — LXT6234
Contents
1.0
2.0
3.0
Block Diagram
.............................................................................................................5
Conscription
.................................................................................................................6
Functional Description
...........................................................................................11
3.1
Frame Format......................................................................................................11
3.2
HDB3 Codecs......................................................................................................11
3.3
HDB3 Decoder Alarms........................................................................................12
3.4
Multiplexer...........................................................................................................12
3.4.1
Flag Bits .................................................................................................13
3.4.2
Multiplexer Alarms..................................................................................14
3.5
Demultiplexer ......................................................................................................14
3.5.1
Demultiplexer Alarms.............................................................................14
Glossary
.......................................................................................................................16
Application Information
.........................................................................................17
5.1
E1/E3 Multiplexer Block Diagram........................................................................17
5.1.1
E1 Line Interface....................................................................................17
5.1.2
LXT6234, E1/E2 Stage...........................................................................17
5.1.3
LXT6234, E3 Stage................................................................................18
Test Specifications
..................................................................................................19
AC Timing Specifications
.....................................................................................20
4.0
5.0
6.0
7.0
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
Block Diagram.......................................................................................................5
LXT6234 Pin Assignment......................................................................................6
Multiplexer Side Block Diagram ..........................................................................12
E2 Frame.............................................................................................................13
E3 Frame.............................................................................................................13
Demultiplexer Side Block Diagram......................................................................15
E1/E3 Multiplexer Block Diagram........................................................................17
HDB3 Encoder and Decoder Timing (Refer to
Table 5
)......................................20
Multiplexer Tributary Input Timing (Refer to
Table 6
)..........................................20
High Speed Multiplexer Input & Output Timing (Refer to
Table 7
) ......................21
High Speed Demultiplexer Input & Output Timing (Refer to
Table 8
)..................22
Chip Enable Timing (Refer to
Table 9
)................................................................22
Package Specifications.......................................................................................23
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