參數(shù)資料
型號(hào)： LXT386
廠商： Intel Corp.
英文描述： QUAD T1/E1/J1 Transceiver
中文描述： 四T1/E1/J1收發(fā)器
文件頁(yè)數(shù)： 5/78頁(yè)
文件大?。?/td> 500K
代理商： LXT386
Datasheet
5
QUAD T1/E1/J1 Transceiver
—
LXT386
35
36
37
Output Jitter for CTR12/13 applications..............................................................75
60 Plastic Ball Grid Array (PBGA) Package Dimensions....................................76
100 Pin Low Quad Flat Packages (LQFP) Dimensions ......................................77
Tables
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Pin Assignments and Signal Descriptions...........................................................11
Line Length Equalizer Inputs...............................................................................27
Jitter Attenuation Specifications..........................................................................30
Operation Mode Summary..................................................................................34
Microprocessor Parallel Interface Selection........................................................35
Serial and Parallel Port Register Addresses.......................................................38
Register Bit Names .............................................................................................38
ID Register, ID (00H)...........................................................................................39
Analog Loopback Register, ALOOP (01H)..........................................................39
Remote Loopback Register, RLOOP (02H)........................................................40
TAOS Enable Register, TAOS (03H)..................................................................40
LOS Status Monitor Register, LOS (04H) ...........................................................40
DFM Status Monitor Register, DFM (05H)..........................................................40
LOS Interrupt Enable Register, LIE (06H)...........................................................40
DFM Interrupt Enable Register, DIE (07H)..........................................................40
LOS Interrupt Status Register, LIS (08H)............................................................41
DFM Interrupt Status Register, DIS (09H)...........................................................41
Software Reset Register, RES (0AH)..................................................................41
Performance Monitoring Register, MON (0BH)...................................................41
Digital Loopback Register, DL (0CH)..................................................................41
LOS/AIS Criteria Register, LCS (0DH)................................................................41
Automatic TAOS Select Register, ATS (0EH).....................................................42
Global Control Register, GCR (0FH)...................................................................42
Pulse Shaping Indirect Address Register, PSIAD (10H).....................................43
Pulse Shaping Data Register, PSDAT (11H)......................................................43
Output Enable Register, OER (12H)...................................................................43
AIS Status Monitor Register, AIS (13H)..............................................................43
AIS Interrupt Enable Register, AISIE (14H) ........................................................44
AIS Interrupt Status Register, AISIS (15H) .........................................................44
TAP State Description.........................................................................................46
Device Identification Register (IDR)....................................................................50
Analog Port Scan Register (ASR).......................................................................51
Instruction Register (IR) ......................................................................................51
Absolute Maximum Ratings.................................................................................53
Recommended Operating Conditions.................................................................53
DC Characteristics ..............................................................................................54
E1 Transmit Transmission Characteristics..........................................................55
E1 Receive Transmission Characteristics...........................................................55
T1 Transmit Transmission Characteristics..........................................................56
T1 Receive Transmission Characteristics...........................................................57
Jitter Attenuator Characteristics..........................................................................58
Analog Test Port Characteristics.........................................................................59
Transmit Timing Characteristics..........................................................................59
Receive Timing Characteristics...........................................................................60
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