參數(shù)資料
型號： LXT386
廠商： Intel Corp.
英文描述： QUAD T1/E1/J1 Transceiver
中文描述： 四T1/E1/J1收發(fā)器
文件頁數(shù)： 4/78頁
文件大?。?/td> 500K
代理商： LXT386
LXT386 —
QUAD T1/E1/J1 Transceiver
4
Datasheet
5.3
5.4
TAP Controller.....................................................................................................45
JTAG Register Description..................................................................................47
5.4.1
Boundary Scan Register (BSR)..............................................................48
Device Identification Register (IDR)....................................................................50
5.5.1
Bypass Register (BYR) ..........................................................................50
5.5.2
Analog Port Scan Register (ASR)..........................................................50
5.5.3
Instruction Register (IR) .........................................................................51
Test Specifications
..................................................................................................53
6.1
Recommendations and Specifications................................................................75
Mechanical Specifications
...................................................................................76
5.5
6.0
7.0
Figures
1
2
3
LXT386 Block Diagram .........................................................................................7
LXT386 Detailed Block Diagram...........................................................................8
LXT386 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and Pack-
age Markings.........................................................................................................9
LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments...........................10
Pullup Resistor to RESET...................................................................................23
50% AMI Encoding..............................................................................................26
External Transmit/Receive Line Circuitry............................................................29
Jitter Attenuator Loop..........................................................................................31
Analog Loopback ................................................................................................31
Digital Loopback..................................................................................................32
Remote Loopback...............................................................................................32
TAOS Data Path .................................................................................................33
TAOS with Analog Loopback..............................................................................33
Serial Host Mode Timing.....................................................................................37
LXT386 JTAG Architecture .................................................................................45
JTAG State Diagram...........................................................................................47
Analog Test Port Application...............................................................................52
Transmit Clock Timing Diagram..........................................................................59
Receive Clock Timing Diagram...........................................................................60
JTAG Timing .......................................................................................................61
Non-Multiplexed Intel Mode Read Timing...........................................................62
Multiplexed Intel Read Timing.............................................................................63
Non-Multiplexed Intel Mode Write Timing ...........................................................64
Multiplexed Intel Mode Write Timing...................................................................65
Non-Multiplexed Motorola Mode Read Timing....................................................66
Multiplexed Motorola Mode Read Timing............................................................67
Non-Multiplexed Motorola Mode Write Timing....................................................68
Multiplexed Motorola Mode Write Timin..............................................................69
Serial Input Timing ..............................................................................................70
Serial Output Timing ...........................................................................................70
E1, G.703 Mask Templates.................................................................................71
T1, T1.102 Mask Templates ...............................................................................72
LXT386 Jitter Tolerance Performance ................................................................73
Jitter Transfer Performance ................................................................................74
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