參數(shù)資料
型號： LXT334&LXT304A
英文描述： LXT334 & LXT304A - LXT334 & LXT304A ?Low Cost & High Performance Quad E1 Interface Solution
中文描述： LXT334
文件頁數(shù)： 10/32頁
文件大?。?/td> 395K
代理商： LXT334&LXT304A
LXT331
—
Dual T1/E1 Line Interface Unit
10
Datasheet
2.0
Functional Description
The LXT331 is a Dual Line Interface Unit (DLIU), which contains two ports. Refer to the
simplified block diagram on page 1. The DLIU is designed for both 1.544 Mbps (DSX-1) and
2.048 Mbps (E1) applications. Both ports operate at the same frequency, which is determined by
the TCLK input.
Each port’s front end interfaces with two lines, one line for transmit, one line for receive. These
two lines comprise a digital data loop for full-duplex transmission. Each port’s back-end interfaces
with a layer processor through bipolar data I/O channels.
The DLIU may either be controlled by a microprocessor via the serial port (Host mode), or by
hardwired pins for stand-alone operation (Hardware mode).
2.1
Receiver
The two receivers in the LXT331 DLIU are identical. The following paragraphs describe the
operation of a single receiver.
The input signal is received via a 1:1 transformer. The receiver requires fully differential inputs
which are internally self-biased into 2.5 V. Recovered data is output at PMRK and NMRK. Refer to
Test Specifications for receiver timing.
The receive signal is processed through an adaptive peak detector and data slicers. The peak
detector samples the received signal and determines its maximum value. A percentage of the peak
value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio.
For DSX-1 applications (line length inputs LEN0-LEN2
≠
000 or 001), the threshold is set to 70%
(typical) of the peak value.
This threshold is maintained above the specified level for up to 15 successive zeros over the range
of specified operating conditions. For E1 applications (LEN0-LEN2 = 000 or 001) the threshold is
50% (typical).
The receiver is capable of accurately recovering signals with up to +13.6 dB of attenuation (from
2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is
1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level,
the peak detectors are held above a minimum level of 0.3 V (typical) to provide immunity from
impulsive noise. Built in pulse stretching circuitry maintains a minimum positive and negative
mark pulse width (see
Table 13
and
Figure 15 on page 28
).
2.2
Transmitter
The two transmitters in the LXT331 DLIU are identical. The following paragraphs describe the
operation of a single transmitter.
Transmit data is clocked serially into the device at TPOS/TNEG. Input synchronization is supplied
by the transmit clock (TCLK). The TPOS/TNEG inputs are sampled on the falling edge of TCLK.
If TCLK is held Low, the transmitter remains powered down and the TTIP/TRING outputs are held
in a high-Z state (except in TAOS mode if MCLK is available). Each output driver is provided with
相關(guān)PDF資料
PDF描述
LXT336QE PCM RECEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|64PIN|PLASTIC
LXT350PE PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC
LXT361LE Telecommunication IC
LXT361PE Telecommunication IC
LXT362LE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT335 制造商:LVL1 制造商全稱:LVL1 功能描述:Quad Short Haul PCM Analog Interface
LXT336QE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM RECEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|64PIN|PLASTIC
LXT350 制造商:LVL1 制造商全稱:LVL1 功能描述:Integrated T1/E1 S/H Transceivers With Crystal-less Jitter Attenuation
LXT350PE 制造商:Intel 功能描述:
LXT350QE 制造商:LEVEL1 功能描述:
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