- 您現(xiàn)在的位置：買賣IC網 > PDF目錄369884 > LXT1000 LAN TRANSCEIVER|SINGLE|HYBRID|BGA|492PIN|PLASTIC PDF資料下載
參數(shù)資料
| 型號： | LXT1000 |
| 英文描述： | LAN TRANSCEIVER|SINGLE|HYBRID|BGA|492PIN|PLASTIC |
| 中文描述： | 網絡收發(fā)器|單|混合|的BGA | 492PIN |塑料 |
| 文件頁數(shù)： | 16/104頁 |
| 文件大?。?/td> | 1500K |
| 代理商： | LXT1000 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
LXT1000
—
Gigabit Ethernet Transceiver
16
Datasheet
Y22
DUPLEX/
TX_TCLKN
I, MD
Duplex Mode.
When 21.15 = 0 (default), this input
controls the duplex state of
the link. Its exact function varies depending on the state of AN_EN. For TBI
configurations, this input should be tied High.
When AN_EN is High, this bit enables advertising of full-duplex capabilities. (Bits
9.9, 4.8, and 4.6 are set High if the corresponding SPEED is also High).
When AN_EN is Low, this bit directly forces duplex state through MII bit 0.8; Low
= half duplex; High = full duplex.
O
TX_TCLKN (Transmit Jitter Test Clock)
. The internal 125 MHz clock used to
transmit data is output as a differential signal on Y22 and AA22 when 21.15 = 1.
L2
AN_RSTRT
I, MD
Restart Auto Negotiation.
A positive edge on AN_RSTRT restarts the Auto-
negotiation process. This signal controls the MII Control Register bit 0.9.
AN_RSTRT is relevant only when AN_EN is High.
R23
SMART_SPD
LHR
Smart Speed Select.
When High, this input enables SmartSpeed control.
SMART_SPD drives bit 16.7 (see
“
SmartSpeed
”
on page 43
).
AA22
PAUSE/
TX_TCLKP
I, MD
O
Pause Configuration
. When 21.15 = 0 (default), this input determines the
settings of Pause (4.10) and ASM_DIR (4.11) during auto-negotiation. If this input
is High, both bits are set High; if Low, both are disabled.
TX_TCLKP (Transmit Jitter Test Clock)
. The internal 125 MHz clock used to
transmit data is output as a differential signal on Y22 and AA22 when 21.15 = 1.
B21
MASTER
I, MD
Master/Slave Configuration
. This configuration sets Port Type bit 9.10, which
indicates the Gigabit Master/Slave configuration. The default configuration, bit
9.12, interprets this setting as the preferred, but not required, mode.
High = Master (multi-port) configuration (Transmitter driven from local clock
source).
Low = Slave (single-port) configuration. (Transmitter driven from recovered clock).
T22
CROSS
I, MD
Crossover Selection.
Determines TPAP/N and TPBP/N operation during auto-
negotiation and 10/100 operation. Crossover Selection is not used during 1000
operation.
When High, TPAP/N is an input; TPBP/N is an output (Switch configuration).
When Low, TPAP/N is an output; TPBP/N is an input (NIC/DTE configuration).
When set to mid-level voltage or left open, the device automatically determines
correct operation. Changing the state of this input generates an internal reset,
resulting in a new auto-negotiation cycle.
M24
ANISOL
LHR
Auto Negotiate Isolate.
When ANISOL is High, the auto-negotiation isolate
feature is enabled (refer to
“
Auto-Negotiate Isolation
”
on page 43
). ANISOL
drives 16.2.
M22
SER10
LHR
Serial Mode.
Applies when the MAC interface is used in the GMII configuration.
Determines how 10 Mbps links are handled and setting of bit 16.3:
GMII Configuration:
High = Serial mode (1 bit x 10 MHz)
Low = MII mode (4 bits x 2.5 MHz).
TBI Configuration:
For TBI configuration, pull Low.
U24
TBI
CONFIGURATI
ON
LHR
Ten-Bit Interface (TBI) Mode.
Determines MAC interface configuration and
setting of bit 16.1.
High = TBI Configuration
Low = GMII configurations.
Table 4. LXT1000 Configuration Signal Descriptions
(Continued)
Ball #
Symbol
Type
1
Description
2
1. I/O Column Coding: LHR = Input, Latched on Low-to-High edge of RESET (ignored thereafter); I, MD = Input, Latched on
Low-to-High edge of RESET, used thereafter only if Manual Control mode (MDDIS = 1).
2. MAC Interface Operating modes: GMII (1000 Mbps), MII (10 or 100 Mbps), Serial (10 Mbps).
相關PDF資料 |
PDF描述 |
|---|---|
| LXT19908 | Amplifier. Other |
| LXT300JE | PCM Transceiver |
| LXT300NE | PCM Transceiver |
| LXT300PE | PCM Transceiver |
| LXT300ZNE | PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|DIP|28PIN|PLASTIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LXT10000 | 制造商:Red Lion Controls 功能描述:ANNUNCIATOR LABELS, 1 LPAX LABEL: T 制造商:Red Lion Controls 功能描述:1 LPAX LABEL T |
| LXT1001BC | 制造商:Level One 功能描述:ELECTRONIC COMPONENT |
| LXT13002D WAF | 制造商:Intel 功能描述: |
| LXT14003D | 制造商:Intel 功能描述: |
| LXT14003D DIE | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。