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參數(shù)資料
| 型號： | LVT22V10-DD |
| 英文描述： | Fuse-Programmable PLD |
| 中文描述： | 保險絲，可編程的PLD |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 185K |
| 代理商： | LVT22V10-DD |
Philips Semiconductors
Product specification
LVT22V10
3V high speed, universal PLD device
1998 Feb 10
6
AC ELECTRICAL CHARACTERISTICS
Over commercial operating temperature range.
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
MIN
TYP
MAX
Input or feedback to non-reg
2
PLCC package
Active-LOW
7.5
ns
t
PD
Active-HIGH
7.5
ns
Input or feedback to non-reg
2
DIP and SOL packages
Active-LOW
8.0
ns
Active-HIGH
8.0
ns
t
S
Setup time from input, feedback or SP to Clock
5.5
ns
t
H
Hold time
0
ns
t
CO
Clock to output
5.0
ns
t
CF
Clock to feedback
3
3.0
ns
t
AR
Asynchronous Reset to registered output
12.0
ns
t
ARW
Asynchronous Reset width
5.0
ns
t
ARR
Asynchronous Reset recovery time
5.0
ns
t
SPR
Synchronous Preset recovery time
5.0
ns
t
WL
Width of Clock LOW
3.0
ns
t
WH
Width of Clock HIGH
3.0
ns
f
MAX
Maximum frequency;
External feedback 1/(t
S
+ t
CO
)
4
95
MHz
Maximum frequency;
Internal feedback 1/(t
S
+ t
CF
)
4
Input to Output Enable
5
118
MHz
t
EA
8.5
ns
t
ER
Capacitance
6
Input to Output Disable
5
8.5
ns
C
IN
Input Capacitance (Pin 1)
V
IN
= 2.0V
V
CC
= 3.3V,
T
amb
= 25
°
C,
f = 1MHz
6
pF
Input Capacitance (Others)
V
IN
= 2.0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 2.0V
8
pF
NOTES:
1. Test Conditions: R
= 500
, R
=500
2. t
is tested with switch S
1
open and C
L
= 50pF (including jig capacitance). V
IH
= 3V, V
IL
= 0V, V
T
= 1.5V.
3. Calculated from measured f
internal.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
5. For 3-State output; output enable times are tested with C
L
= 50pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.3V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.3V) level with S
1
closed.
6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
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