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參數(shù)資料
| 型號： | LVT22V10-DD |
| 英文描述： | Fuse-Programmable PLD |
| 中文描述： | 保險絲，可編程的PLD |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 185K |
| 代理商： | LVT22V10-DD |
Philips Semiconductors
Product specification
LVT22V10
3V high speed, universal PLD device
1998 Feb 10
16
“AND” ARRAY – (I, B)
I, B
P, D
CODE
O
STATE
INACTIVE
1
CODE
STATE
CODE
STATE
CODE
STATE
TRUE
H
L
—
P, D
I, B
I, B
P, D
I, B
I, B
P, D
I, B
I, B
I, B
COMPLEMENT
DON’T CARE
SP00008
I, B
I, B
I, B
I, B
NOTE:
1. This is the initial state.
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to
LOW after the device has been powered up. The output state will
depend on the programmed pattern. This feature is valuable in
simplifying state machine initialization. A timing diagram and
parameter table are shown below. Due to the synchronous operation
of the power-up reset and the wide range of ways V
CC
can rise to its
steady state, two conditions are required to ensure a valid power-up
reset. These conditions are:
1. The V
CC
rise must be monotonic.
2. Following reset, the clock input must not be driven from LOW to
HIGH until all applicable input and feedback setup times are met.
t
WL
Power-Up Reset Waveform
2.7V
V
CC
t
S
t
PR
POWER
REGISTERED
ACTIVE-LOW
OUTPUT
CLOCK
SP00389
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
PR
Power-up Reset Time
1
μ
s
t
S
Input or Feedback Setup Time
See AC Electrical
t
WL
Clock Width LOW
Characteristics
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