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參數(shù)資料
| 型號(hào)： | LVT22V10-DD |
| 英文描述： | Fuse-Programmable PLD |
| 中文描述： | 保險(xiǎn)絲，可編程的PLD |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 185K |
| 代理商： | LVT22V10-DD |
Philips Semiconductors
Product specification
LVT22V10
3V high speed, universal PLD device
1998 Feb 10
13
OUTPUT MACRO CELL
F
0
1
1
0
0
1
0
0
1
CLK
1
AR
SP
S
1
S
0
S
1
S
0
OUTPUT CONFIGURATION
0 = Unprogrammed fuse
1 = Programmed fuse
D
Q
Q
0
0
1
1
0
1
0
1
Registered/Active-LOW
Registered/Active-HIGH
Combinatorial/Active-LOW
Combinatorial/Active-HIGH
SP00375
Figure 2.
Output Macro Cell Logic Diagram
F
CLK
AR
SP
S
0
= 0
S
1
= 0
D
Q
Q
a. Registered/Active-LOW
F
CLK
AR
SP
S
0
= 1
S
1
= 0
D
Q
Q
b. Registered/Active-HIGH
F
S
0
= 0
S
1
= 1
c. Combinatorial/Active-LOW
d. Combinatorial/Active-HIGH
F
S
0
= 1
S
1
= 1
SP00376
Figure 3.
Output Macro Cell Configurations
Registered Output Configuration
Each Macro Cell of the LVT22V10 includes a D-type flip-flop for data
storage and synchronization. The flip-flop is loaded on the
LOW-to-HIGH transition of the clock input. In the registered
configuration (S
1
= 0), the array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any Macro Cell can be configured as combinatorial by selecting the
multiplexer path that bypasses the flip-flop (S
1
= 1). In the
combinatorial configuration, the feedback is from the pin.
Variable Input/Output Pin Ratio
The LVT22V10 has twelve dedicated input lines, and each Macro
Cell output can be an I/O pin. Buffers for device inputs have
complementary outputs to provide user-programmable input signal
polarity.
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