參數(shù)資料
型號(hào)： LV8572AMX
英文描述： Real-Time Clock
中文描述： 實(shí)時(shí)時(shí)鐘
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 353K
代理商： LV8572AMX
Functional Description
(Continued)
D0 and D1:
These bits are available as general purpose
RAM.
D2:
This bit, when set to a one makes the INTR output pin
active high, and when set to a zero, it makes this pin active
low.
D3:
This bit controls whether the INTR pin is an open drain
or push-pull output. A one indicates push-pull.
D4:
This bit, when set to a one makes the MFO output pin
active high, and when set to a zero, it makes this pin active
low.
D5:
This bit controls whether the MFO pin is an open drain
or push-pull output. A one indicates push-pull.
D6 and D7:
These bits are used to program the signal ap-
pearing at the MFO output, as follows:
D7
D6
MFO Output Signal
0
0
1
0
1
X
2nd Interrupt
Timer 0 Waveform
Buffered Crystal Oscillator
INTERRUPT CONTROL REGISTER 0
TL/F/11416–22
D0–D5:
These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subse-
quent interrupts will be spaced correctly. These interrupts
are useful when minute, second, real time reading, or task
switching is required. When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin.
D6 and D7:
These are individual timer enable bits. A one
written to these bits enable the timers to generate interrupts
to the
m
P.
INTERRUPT CONTROL REGISTER 1
TL/F/11416–23
D0–D5:
Each of these bits are enable bits which will enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the ‘‘a(chǎn)lways equal’’ state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit D3 of the Main Status Regis-
ter, all bits must be written to a logic zero.
D6:
In order to generate an external alarm compare inter-
rupt to the
m
P from bit D3 of the Main Status Register, this
bit must be written to a logic 1. If battery backed mode is
selected then this bit is controlled by D4 of the Real Time
Mode Register.
D7:
The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the
m
P when PFAIL
e
0. If battery backed
mode is selected then this bit is controlled by D4 of the Real
Time Mode Register.
This bit also enables the low battery detection analog cir-
cuitry.
If the user wishes to mask the power fail interrupt, but utilize
the analog circuitry, this bit should be enabled, and the
Routing Register can be used to route the interrupt to the
MFO pin. The MFO pin can then be left open or configured
as the Timer 0 or buffered oscillator output.
19
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