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參數(shù)資料
| 型號(hào)： | LV320MH |
| 廠商： | Spansion Inc. |
| 英文描述： | 32 Megabit (4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| 中文描述： | 32兆位（4個(gè)M × 8位）的MirrorBit⑩3.0伏特，只有統(tǒng)一部門閃存記憶體與VersatileI /輸出⑩控制 |
| 文件頁數(shù)： | 27/61頁 |
| 文件大?。?/td> | 772K |
| 代理商： | LV320MH |
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September 12, 2006
Am29LV033MU
25
D A T A S H E E T
sequence.
Note that the SecSi Sector, autoselect, and
CFI functions are unavailable when a program opera-
tion is in progress.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the
Write Operation
Status
section for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
Note that a
hardware reset
immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from “0” back to a “1.”
Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Note: Single byte programming is not supported in x8-mode.
Write buffer programming must be used during x8-mode
operation.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 10 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
Write Buffer Programming
Write buffer programming allows the system to write a
maximum of 32 bytes in one programming operation.
The effective programming time is faster than the stan-
dard programming algorithms. The write buffer pro-
gramming command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle containing the Write Buffer Load command
written at the Sector Address in which programming
will occur. The fourth cycle writes the sector address
and the number of byte locations, minus one, to be
programmed. For example, if the system will program
6 unique address locations, then 05h should be written
to the device. This tells the device how many write
buffer addresses will be loaded with data and therefore
when to expect the Program Buffer to Flash command.
The number of locations to program cannot exceed
the size of the write buffer or the operation will abort.
The fifth cycle writes the first address location and
data to be programmed. A write-buffer-page is se-
lected by address bits A
MAX
–A
5
. All subsequent ad-
dress/data
pairs
must
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
fall
within
the
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer. That
is, write buffer programming cannot occur across mul-
tiple write-buffer pages or sectors. If the system at-
tempts to load programming data outside of the
selected write-buffer page, the operation will abort.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
system must therefore account for loading a
write-buffer location more than once. The counter dec-
rements for each data load operation, not for each
unique write-buffer-address location. Additionally, the
last data loaded prior to the Program Buffer to Flash
command will be programmed into the device. Note
also that if an address location is loaded more than
once into the buffer, the final data loaded for that ad-
dress will be programmed.
Once the specified number of write buffer locations
have been loaded, the system must then write the Pro-
gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.
The write-buffer programming operation can be sus-
pended using the standard program suspend/resume
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