- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369872 > LU5X34F Quad Gigabit Ethernet Transceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | LU5X34F |
| 英文描述： | Quad Gigabit Ethernet Transceiver |
| 中文描述： | 四個(gè)千兆以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 445K |
| 代理商： | LU5X34F |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
5
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Functional Description
(continued)
Powerup Sequence
The power ramp time for the LU5X34F is specified at
V
DD
> 2.7 V within 20 μs of start-up. Once 2.7 V is
reached, the device is held in reset for 15 μs—70 μs.
The REFCLK must be active and within specification at
this point and remain active while the device is pow-
ered up, unless in Reset.
When signals RESET, BYPPLL, and LPWR are all low,
the following start-up sequence occurs:
1. 0 μs—32 μs, the analog PLL is held at minimum fre-
quency to allow dc bias to settle.
2. 32 μs—262 μs, the analog PLL has locked-in and
receiver analog circuits start to lock-in.
3. 262 μs—326 μs, the receiver analog circuits are
locked; receiver starts to lock onto incoming data.
4. After 358 μs, the receiver is locked onto incoming
data and can be viewed at the parallel output ports.
The comma-detect circuit is enabled at this point,
allowing byte alignment if ENCDET = 1.
If LCKREFN goes low after the 358 μs, the receiver will
sit idle. When LCKREFN goes high, the receiver will be
locked onto data after 2 μs.
Device Reset
The RESETN input to the device is active-low. When
activated with a pulse duration of 1 μs, the RESETN sig-
nal globally resets the device and the following is per-
formed:
1. The single analog PLL is forced to operate at the mini-
mum frequency possible for its VCO. The PLL will not
be locked in this condition.
2. The HDOUTP HDOUTN outputs are forced to a
PECL logic 0.
3. The deserializer clocks, but input data at HDINP,
HDINN is ignored and the RX[9:0] signals remain in
their previous state.
4. The phase interpolation/selection circuits are deacti-
vated and the selected phase is reset.
5. The receiver digital low-pass filter in the DPLL is reset.
Normally, a reset is not necessary for correct operation,
although a reset can aid rapid lock-in of the internal
PLL circuitry. This active-low pin is internally pulled
high.
Sleep Mode
The LU5X34F has a sleep mode that is activated by
enabling LPWR. In this mode, a divided-down version
of the REFCLK is used to refresh the dynamic circuits
within the transceiver. The PLL is powered down in this
mode also. LCKREFN can also be activated to reduce
the power even further. Note that complete powerdown
for I
DD
Q testing is not supported due to the dynamic
logic used in the high-speed sections of the trans-
ceiver. The lock-in sequence timing is needed when
coming out of sleep mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU5X34F | Quad Gigabit Ethernet Transceiver(千兆位以太網(wǎng)四收發(fā)器) |
| LUCL8551AAU | Subscriber Line Interface Circuit |
| LUCL8551AP | Subscriber Line Interface Circuit |
| LUCL8560AAU | Subscriber Line Interface Circuit |
| LUCL8560AU | Subscriber Line Interface Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU5Y041XLF | 制造商:BOTHHAND 制造商全稱:Bothhand USA, LP. 功能描述:1×5 RJ45 CONNECTOR MODULE WITH INTEGRATED 10/100 BASE-TX MAGNETICS |
| LU6000F0 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:16-Bit Single-Chip Microcomputers (With Built-In Flash Memory) |
| LU6000F1 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:16-Bit Single-Chip Microcomputers (With Built-In Flash Memory) |
| LU600Z | 制造商:SEOUL 制造商全稱:Seoul Semiconductor 功能描述:GREEN OVAL LAMP LED |
| LU601 | 制造商:SEOUL 制造商全稱:Seoul Semiconductor 功能描述:BLUE OVAL LAMP LED |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。