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參數資料
| 型號： | LU5X34F |
| 英文描述： | Quad Gigabit Ethernet Transceiver |
| 中文描述： | 四個千兆以太網收發(fā)器 |
| 文件頁數： | 10/26頁 |
| 文件大小： | 445K |
| 代理商： | LU5X34F |
10
Lucent Technologies Inc.
LU5X34F
Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet
July 2000
Input/Output Information
(continued)
Table 3b. Pinout—Channel B I/O
Name
Pin
A4
B5
C6
A5
B6
A6
C7
D7
B7
A7
B3
A2
A1
B1
C2
D3
E4
C1
D2
F4
D6
I/O
Input
Level
TTL/
CMOS
Description
TXB9
TXB8
TXB7
TXB6
TXB5
TXB4
TXB3
TXB2
TXB1
TXB0
RXB9
RXB8
RXB7
RXB6
RXB5
RXB4
RXB3
RXB2
RXB1
RXB0
TXCLKB
Channel B
,
Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked-in on the rising edge of TXCLKB.
TXB0 is the LSB.
Output
TTL/
CMOS
Channel B, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clocked-
out on the alternate rising edge of RXCLK0B,
RXCLK1B. RXB0 is the LSB.
Input
TTL/
CMOS
Transmit Clock (100 MHz—125 MHz).
Used to latch TXB[9:0] data into the LU5X34F.
Synchronous with REFCLK(N)
Channel B, Byte-Align Clock 0.
RXCLK0B
A3
Output
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
PECL
RXCLK1B
B4
Output
Channel B, Byte-Align Clock 1.
ENCDETB
G3
Input
Channel B, Enable Comma Detect.
COMDETB
C4
Output
Channel B, Byte-Aligned Comma.
EWRAPB
F2
Input
Channel B, Loopback at Serial I/O.
LCKREFNB
F1
Input
Channel B, Lock Receiver to Clock.
HDINBP
HDINBN
HDOUTBP
HDOUTBN
LDSTB
F15, E17
Input
Channel B, Differential Serial Inputs.
G14, G15
Output
PECL
Channel B, Differential Serial Outputs.
G4
Input
TTL/
CMOS
Channel B, Load TEST[5:1] inputs.
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