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參數(shù)資料
| 型號： | LU3X54FTL |
| 英文描述： | QUAD-FET for 10Base-T/100Base-TX/FX |
| 中文描述： | 四核10Base-T/100Base-TX/FX場效應(yīng)管 |
| 文件頁數(shù)： | 37/54頁 |
| 文件大?。?/td> | 677K |
| 代理商： | LU3X54FTL |
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Lucent Technologies Inc.
37
Data Sheet
July 2000
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
MII Station Management
(continued)
Management Registers (MR)
(continued)
Table 20. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write.
Register/Bit
1
29.15 (LOCALRST)
Type
2
R/W
Description
Management Reset.
This is the local management reset bit. Writing a logic 1 to
this bit will cause register (zero) 0 and registers 28 and 29 to be reset to their
default values. This bit is self-clearing. Default state is 0.
Generic Reset 1.
This register is used for manufacture test only. Default state is 0.
Generic Reset 2.
This register is used for manufacture test only. Default state is 0.
100 Mbits/s Transmitter Off.
When this bit is set to 0, it forces TPOUT+[D:A] low
and TPOUT–[D:A] high. This bit defaults to 1.
Reserved.
Program to zero.
Carrier Sense Select.
CRS will be asserted on receive only when this bit is set to
a 1. If this bit is set to logic 0, CRS will by asserted on receive or transmit. This bit
is ORed with the H_DUPLED[B] pin during powerup and reset. Default state is 0.
Link Error Indication.
When this bit is a 1, a link error code will be reported on
RXD[3:0] of the LU3X54FT when RX_ER is asserted on the MII. The specific error
codes are listed in the RXD pin description. If it is 0, it will disable this function.
Default state is 0.
Packet Error Indication Enable.
When this bit is a 1, a packet error code, which
indicates that the scrambler is not locked, will be reported on RXD[3:0] of the
LU3X54FT when RX_ER is asserted on the MII. When this bit is 0, it will disable
this function. Default state is 0.
Pulse Stretching.
When this bit is set to 1, the COLED[D:A], TXLED[D:A], and
RXLED[D:A] output signal will be stretched between approximately 42 ms—84 ms.
If this bit is set to 0, it will disable this feature. Default state is 1.
Encoder/Decoder Bypass.
When this bit is set to 1, the 4B/5B encoder and
5B/4B decoder function will be disabled. This bit is ORed with the TXLED[C] pin
during powerup and reset. Default state is 0.
Symbol Aligner Bypass.
When this bit is set to 1, the aligner function will be dis-
abled. Default state is 0.
Scrambler/Descrambler Bypass.
When this bit is set to 1, the scrambling/
descrambling functions will be disabled. This bit is ORed with the TXLED[B] pin
during powerup and reset. Default state is 0.
Carrier Integrity Enable.
When this bit is set to a 1, carrier integrity is enabled.
This bit is ORed with the TXLED[D] pin during powerup and reset. Default state
is 0.
Jam Enable.
When this bit is a 1, it enables JAM associated with carrier integrity
to be ORed with COL. Default state is 0.
Far-End Fault Enable.
This bit is used to enable the far-end fault detection and
transmission capability. This capability may only be used if autonegotiation is dis-
abled. This capability is to be used only with media which does not support auto-
negotiation. Setting this bit to 1 enables far-end fault detection and generation.
Logic 0 will disable the function. Default state is 0.
FX Mode Enable.
When set high, this bit will enable the FX mode (10Base-T and
100Base-TX disabled). When low, it will enable 10Base-T and 100Base-TX mode
(100Base-FX mode disabled). This bit defaults to zero. It is ORed with the FX
mode enable pin.
29.14 (RST1)
29.13 (RST2)
29.12 (100OFF)
R/W
R/W
R/W
29.11 (RESERVED)
29.10 (CRS_SEL)
R/W
R/W
29.9 (LINK_ERR)
R/W
29.8 (PKT_ERR)
R/W
29.7 (PULSE_STR)
R/W
29.6
(ENC_DEC_BYPASS)
R/W
29.5 (SAB)
R/W
29.4
(SCRAM_DESC_BYPASS)
R/W
29.3 (CARIN_EN)
R/W
29.2 (JAM_COL)
R/W
29.1 (FEF_EN)
R/W
29.0 FX_MODE_EN
R/W
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