參數(shù)資料
型號： LU3X54FTL
英文描述： QUAD-FET for 10Base-T/100Base-TX/FX
中文描述： 四核10Base-T/100Base-TX/FX場效應(yīng)管
文件頁數(shù)： 27/54頁
文件大小： 677K
代理商： LU3X54FTL
Lucent Technologies Inc.
27
Data Sheet
July 2000
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
191
SPEEDLED[A]/
ISOLATE_MODE
I/O
Speed LED[A].
This pin indicates the operating speed of port A on the
LU3X54FT. A high on this pin indicates 100 Mbits/s operation. A low
indicates 10 Mbits/s operation. External buffers are necessary to drive
the LEDs.
Isolate Mode.
As an input, this pin can be used at powerup or reset to
select the isolate operation mode. If this pin is pulled high through a
4.7 k
resistor, the LU3X54FT will powerup or reset to the isolate
mode. (MII outputs to high-impedance state.)
This pin is internally pulled low through a 50 k
resistor. The default
state is for the LU3X54FT to powerup or reset in a nonisolate mode.
This pin and register bit [10.0] are ORed together during powerup and
reset.
Half-Duplex LED[D].
When this output is high, it indicates half-duplex
mode. When it is low, it indicates full duplex. External buffers are nec-
essary to drive the LEDs. This output is only valid when the link is up.
Full Duplex.
At powerup, this pin may be used to select full-duplex
operation for all four channels by pulling it high through a 4.7 k
resis-
tor, if station management is unavailable. This is the same function as
register 0, bit 8. This pin has an internal 50 k
pull-down resistor to
default to half duplex for normal operation. This input and the register
bit [0.8] are ORed together during powerup and reset. This pin is
ignored when autonegotiation is enabled.
Half-Duplex LED[A].
When this output is high, it indicates half-duplex
mode. When low, it indicates full duplex. External buffers are necessary
to drive the LEDs. This output is only valid when the link is up.
20 MHz Clock Select.
When this signal is pulled high through a
4.7 k
resistor, it will enable the two-clock input mode (20 MHz and
25 MHz). This pin is internally pulled low through a 50 k
resistor to set
the default to internal 20 MHz. When low, this signal enables the single-
clock input mode (25 MHz with 20 MHz clock internally generated).
201
H_DUPLED[D]/
FULL_DUP
I/O
198
H_DUPLED[A]/
CLK20_SEL
I/O
This pin has the same function as register 30, bit 6, if station manage-
ment is unavailable. This input and the register bit [30.6] are ORed
together during powerup and reset.
CMOS Local Symbol Clock.
A 25 MHz clock,
±
100 ppm, 40%—60%
duty cycle.
Crystal Oscillator Input.
A 25 MHz crystal ±25 ppm can be connected
across XTALIN and XTALOUT.
Crystal Oscillator Output.
A 25 MHz crystal ±25 ppm can be con-
nected across XTALIN and XTALOUT. If a single-ended external clock
(LSCLK) is connected to XTALIN, the crystal output pin should be left
floating.
Test Mode Select.
Reserved for manufacturing testing. These pins
should be tied low for normal operation.
87
LSCLK/XTALIN
I
88
XTALOUT
I
55
207—204
MODE[4:0]
I
Pin Information
(continued)
Pin Descriptions
(continued)
Table 7. Miscellaneous Pins
(continued)
Pin
Signal
Type
Description
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