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參數(shù)資料
| 型號(hào)： | LU3X54FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| 中文描述： | 四場效應(yīng)管（快速以太網(wǎng)收發(fā)器）的10Base-T/100Base-TX/FX（應(yīng)用于10基數(shù)- T的和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 29/54頁 |
| 文件大?。?/td> | 677K |
| 代理商： | LU3X54FT |
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Lucent Technologies Inc.
29
Data Sheet
July 2000
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
MII Station Management
Basic Operations
The primary function of station management is to trans-
fer control and status information about the LU3X54FT
to a management entity. This function is accomplished
by the MDC clock input, which has a maximum fre-
quency of 12.5 MHz, along with the MDIO pin. This pin
(112) requires an external 1.5 k
pull-up resistor.
The management interface (MII) uses MDC and MDIO
to physically transport information between the PHY
and the station management entity.
A specific set of registers and their contents (described
in Table 8) defines the nature of the information trans-
ferred across this interface. Frames transmitted on the
MII management interface will have the frame structure
shown in Table 8. The order of bit transmission is from
left to right. Note that reading and writing of the man-
agement register must be completed without interrup-
tion.
Since the LU3X54FT is a four-channel device, each of
the management registers is duplicated four times as
depicted in the functional block diagram shown in
Figure 1. To select a particular channel [D:A], write to
that channel’s unique PHY address as described in
Table 9.
MII Management Frames
The fields and format for management frames are
described in the following tables.
Table 8. MII Management Frame Format
Table 9. MII Management Frames Field Descriptions
Read/Write
(R/W)
R
W
Pre
ST
OP
PHYADD
REGAD
TA
DATA
Idle
1 . . . 1
1 . . . 1
01
01
10
01
AAAAA
AAAAA
RRRRR
RRRRR
Z0
10
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Z
Z
Field
Pre
Description
Preamble
. The preamble is a series of 32 ones. The LU3X54FT will accept frames with no pream-
ble. This is indicated by a 1 in register 1, bit 6.
Start of Frame.
The start of frame is indicated by a 01 pattern.
Operation Code
. The operation code for a read transaction is 10. The operation code for a write
transaction is 01.
PHY Address
. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity, which is
attached to multiple PHY entities, must have prior knowledge of the appropriate PHY address for
each entity. The address 00000 is the broadcast address. This address will produce a match
regardless of the local address.
The LU3X54FT maps the PHYADD[2:0] to the most significant 3 bits, while the least significant
2 bits address the channel within the LU3X54FT as follows:
00: Channel A.
01: Channel B.
10: Channel C.
11: Channel D.
Register Address.
The register address is 5 bits, allowing for 32 unique registers within each PHY.
The first register address bit transmitted and received is the MSB of the address.
Turnaround
. The turnaround time is a 2-bit time spacing between the register address field and the
data field of a frame to avoid drive contention on MDIO during a read transaction. During a write to
the LU3X54FT, these bits are driven to a 10 by the station. During a read, the MDIO is not driven
during the first bit time and is driven to a 0 by the LU3X54FT during the second bit time.
Data
. The data field is 16 bits. The first bit transmitted and received is bit 15 of the register being
addressed.
ST
OP
PHYADD
REGAD
TA
DATA
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相關(guān)代理商/技術(shù)參數(shù) |
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| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208-DB | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208-DB |
| LU400 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:NEMA Cabinet Legs |
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