參數(shù)資料
型號(hào)： LU3X54FT
廠商： Lineage Power
英文描述： Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器)
中文描述： 四場(chǎng)效應(yīng)管（快速以太網(wǎng)收發(fā)器）的10Base-T/100Base-TX/FX（應(yīng)用于10基數(shù)- T的和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 19/54頁(yè)
文件大?。?/td> 677K
代理商： LU3X54FT
Lucent Technologies Inc.
19
Data Sheet
July 2000
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
136
135
134
132
RXD_100[3:0]
O
Shared Receive Data.
4-bit parallel data outputs that are synchronous to the
falling edge of RX_CLK25. When RX_ER is asserted high, an error code will
be presented on RXD_100[3:0] where appropriate. The codes are as follows:
I
Packet errors, ERROR_CODES = 2h.
I
Link errors, ERROR_CODES = 3h (packet and link error codes will only be
repeated if registers [29.9] and [29.8] are enabled).
I
Premature end errors, ERROR_CODES = 4h.
I
Code errors, ERROR_CODES = 5h.
Receive Enable—10 Mbits/s Mode.
When SMART_MODE_SELECT is not
enabled and RX_EN10 is driven high, its channel’s data and clock (RXD0 and
RX_CLK) are driven onto the shared serial bus. If the individual channel is not
configured for 10 Mbits/s mode, this input will be ignored. When RX_EN10s
are all set low, the serial bus will float.
60
59
57
56
RX_EN10[D:A]
I
Note:
Care should be taken that no more than one RX_EN is asserted at a
time.
When SMART_MODE_SELECT is enabled, these pins are ignored.
Receive Enable—100 Mbits/s Mode.
When SMART_MODE_SELECT is not
enabled and RX_EN100 is driven high, its channel’s data, clock, and receive
data valid signals (RXD_100, RX_DV, RX_ER, and RX_CLK25) are driven
onto the shared MII bus. If the individual channel is not configured for
100 Mbits/s mode, this input will be ignored. When RX_EN100s are all set low,
the MII bus will float.
110
78
161
138
RX_EN100[D:A]/
RX_EN10/100[D:A]
I
Note:
Care should be taken that no more than one RX_EN is asserted at a
time.
Receive Enable—10/100 Mbits/s Smart Mode.
When
SMART_MODE_SELECT is asserted and RX_EN100 is driven high, its chan-
nel’s data, clock, and receive data valid signals [RXD, RX_ER (100 Mbits/s
only), RX_DV (100 Mbits/s only), and RX_CLK] are driven onto the shared bus
corresponding to the speed of the channel.
Shared Receive Data Valid.
When this pin is driven high, it indicates that the
LU3X54FT is recovering and decoding valid nibbles on RXD[3:0] and that the
data is synchronous with RX_CLK. RX_DV is synchronous with RX_CLK. This
pin is not used in serial 10 Mbits/s mode.
Shared Receive Error.
When asserted high, it indicates that the LU3X54FT
has detected a coding error in the frame presently being transferred. RX_ER is
synchronous with RX_CLK25. This signal is not used in 10 Mbits/s mode.
Shared Transmit Data.
10 Mbits/s serial input synchronous with TX_CLK10.
Shared Transmit Data.
4-bit parallel input synchronous with TX_CLK25.
128
RX_DV
O
130
RX_ER
O
139
120
119
117
116
TXD_10
TXD_100[3:0]
I
I
Pin Information
(continued)
Pin Descriptions
(continued)
When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII
port B.
Table 4. MII/Serial Interface Pins in Bused MII Mode
(continued)
Pin
Signal
Type
Description
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