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參數(shù)資料
| 型號： | LTC6945IUFD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER INTEGER N 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標準包裝： | 2,500 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
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LTC6945
13
6945f
OPERATION
Figure 7. Simplified RF Interface Schematic
The CPWIDE bit extends the charge pump output current
pulse width by increasing the PFD reset path’s delay value
(see Figure 3). CPWIDE is normally set to 0.
VCO INPUT BUFFER
The VCO frequency is applied differentially on pins VCO+ and
VCO–. The inputs are self-biased and must be AC-coupled.
Alternatively, the inputs may be used single-ended by ap-
plying the VCO frequency at VCO+ and bypassing VCO– to
GND with a capacitor. Each input provides a single-ended
121Ω resistance to aid in impedance matching at high
frequencies. See the Applications Information section for
matching guidelines.
teger from 1 to 6, inclusive, outputting a 50% duty cycle
even with odd divide values. Use the OD[2:0] bits found
in register h08 to directly program the 0 divide ratio. See
the Applications Information section for the relationship
between O and the fREF, fPFD, fVCO and fRF frequencies.
RF OUTPUT BUFFER
The low noise, differential output buffer produces a dif-
ferential output power of –6dBm to 3dBm, settable with
bits RFO[1:0] according to Table 7. The outputs may be
combined externally, or used individually. Terminate any
unused output with a 50Ω resistor to VRF+.
Table 7. RFO[1:0] Programming
RFO[1:0}
PRF (Differential)
PRF (Single-Ended)
0
–6dBm
–9dBm
1
–3dBm
–6dBm
2
0dBm
–3dBm
3
3dBm
0dBm
Each output is open collector with 136Ω pull-up resistors
to VRF+, easing impedance matching at high frequencies.
See Figure 7 for circuit details and the Applications Infor-
mation section for matching guidelines. The buffer may be
muted with either the OMUTE bit, found in register h02,
or by forcing the MUTE input low.
16
15
121Ω
VCO+
VC0–
121Ω
6945 F06
0.9V
VVCO
+
VVCO
+
VVCO
+
–
Figure 6. Simplified VCO Interface Schematic
VCO (N) DIVIDER
The 16-bit N divider provides the feedback from the VCO
input buffer to the PFD. Its divide ratio N may be set to any
integer from 32 to 65535, inclusive. Use the ND[15:0] bits
found in registers h05 and h06 to directly program the N
divide ratio. See the Applications Information section for
the relationship between N and the fREF, fPFD, fVCO and
fRF frequencies.
OUTPUT (O) DIVIDER
The 3-bit O divider can reduce the frequency from the VCO
input buffer to the RF output buffer to extend the output
frequency range. Its divide ratio O may be set to any in-
12
11
6945 F07
VRF
+
VRF
+
RF+
136Ω
RF–
MUTE
OMUTE
RFO[1:0]
9
MUTE
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6946-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-2 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-3 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946IUFD-1#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-1#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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