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參數(shù)資料
| 型號(hào)： | LTC6945IUFD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER INTEGER N 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
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LTC6945
20
6945f
The next step in the algorithm is to determine the open-
loop bandwidth. BW should be at least 10
× smaller than
fPFD. Wider loop bandwidths could have lower integrated
phase noise, depending on the VCO phase noise signature,
while narrower bandwidths will likely have lower spurious
power. Use a factor of 25 for this design:
BW
=
250kHz
25
= 10kHz
Loop Filter Component Selection
Now set loop filter resistor RZ and charge pump current
ICP. Because the KVCO varies over the VCO’s frequency
range, using the KVCO geometric mean gives good results.
Using an ICP of 11.2mA, RZ is determined:
K
VCO = 10
6 15 21.6 = 18MHz / V
R
Z =
2
π 10k 3656
11.2m 18M
R
Z = 1.14k
Now calculate CI and CP from Equations 7 and 8:
C
I =
3.5
2
π 10k 1.14k
= 48.9nF
C
P =
1
7
π 10k 1.14k
= 3.99nF
Status Output Programming
This example will use the STAT pin to monitor a phase
lock condition. Program x[2] = 1 to force the STAT pin
high whenever the LOCK bit asserts:
Reg01 = h04
Power Register Programming
For correct PLL operation all internal blocks should be
enabled, but PDREFO should be set if the REFO pin is
not being used. OMUTE may remain asserted (or the
MUTE pin held low) until programming is complete. For
PDREFO = 1 and OMUTE = 1:
Reg02 = h0A
Divider Programming
Program registers Reg03 to Reg06 with the previously
determined R and N divider values:
Reg03 = h01
Reg04 = h90
Reg05 = h0E
Reg06 = h48
Reference Input Settings and Output Divider
Programming
From Table 1, FILT = 0 for a 100MHz reference frequency.
Next, convert 7dBm into VP-P. For a CW tone, use the
following equation with R = 50:
V
P-P
R 10
(dBm – 21)/20
(9)
This gives VP-P = 1.41V, and, according to Table 2, set
BST = 1.
Now program Reg08, assuming maximum RF± output
power (RFO[1:0] = 3 according to Table 7) and OD[2:0] = 1:
Reg08 = h99
Lock Detect and Charge Pump Current Programming
Next determine the lock indicator window from fPFD. From
Table 3, LKWIN[1:0] = 3 for a tLWW of 90ns. The LTC6945
will consider the loop “l(fā)ocked” as long as the phase
coincidence at the PFD is within 8°, as calculated below:
phase = 360° tLWW fPFD = 360 90n 250k 8°
LKWIN[1:0] may be set to a smaller value to be more
conservative. However, the inherent phase noise of the
loop could cause false “unlocks” for too small a value.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6946-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-2 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-3 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946IUFD-1#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-1#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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