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參數(shù)資料
| 型號： | LTC6945IUFD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER INTEGER N 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標準包裝： | 2,500 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
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LTC6945
18
6945f
APPLICATIONS INFORMATION
INTRODUCTION
A PLL is a complex feedback system that may conceptually
be considered a frequency multiplier. The system multiplies
the frequency input at REF± and outputs a higher frequency
at RF±. The PFD, charge pump, N divider, and external VCO
and loop filter form a feedback loop to accurately control
the output frequency (see Figure 15). The R and O dividers
are used to set the output frequency resolution.
Using the above equations, the output frequency resolution
fSTEP produced by a unit change in N is given by Equation 5:
f
STEP =
f
REF
R O
(5)
LOOP FILTER DESIGN
A stable PLL system requires care in selecting the external
loop filter values. The Linear Technology PLLWizard ap-
plication, available from www.linear.com, aids in design
and simulation of the complete system.
The loop design should use the following algorithm:
1. Determine the output frequency, fRF, and frequency
step size, fSTEP, based on application constraints. Using
Equations 2, 3, 4 and 5, change fREF, N, R and O until
the application frequency constraints are met. Use the
minimum R value that still satisfies the constraints.
2. Select the loop bandwidth BW constrained by fPFD. A
stable loop requires that BW is less than fPFD by at least
a factor of 10.
3. Select loop filter component RZ and charge pump cur-
rent ICP based on BW and the VCO gain factor KVCO.
BW (in Hz) is approximated by the following equation:
BW
I
CP RZ K VCO
2
π N
or :
R
Z =
2
π BW N
I
CP K VCO
(6)
where KVCO is in Hz/V, ICP is in Amps, and RZ is in Ohms.
KVCO is the VCO’s frequency tuning sensitivity, and
may be determined from the VCO specifications. Use
ICP = 11.2mA to lower in-band noise unless component
values force a lower setting.
Figure 15. PLL Loop Diagram
R_DIV
N_DIV
÷R
÷N
÷O
fPFD
LTC6945
REF±
(fREF)
(fVCO)
KPFD
KVCO
RF±
(fRF)
CP
RZ
CI
CP
LOOP FILTER
LF(s)
6945 F15
VCO±
ICP
O_DIV
OUTPUT FREQUENCY
When the loop is locked, the frequency fVCO (in Hz)
produced at the output of the VCO is determined by the
reference frequency fREF, and the R and N divider values,
given by Equation 2:
f
VCO =
f
REF N
R
(2)
Here, the PFD frequency fPFD produced is given by the
following equation:
f
PFD =
f
REF
R
(3)
and fVCO may be alternatively expressed as:
fVCO = fPFD N
The output frequency fRF produced at the output of the O
divider is given by Equation 4:
f
RF =
f
VCO
O
(4)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6946-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-2 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-3 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946IUFD-1#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-1#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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