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參數(shù)資料
| 型號(hào)： | LTC4303CDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 549K |
| 描述： | IC BUS BUFFER I2C 8-DFN |
| 產(chǎn)品培訓(xùn)模塊： | LTC4310 - Hot-Swappable I²C Isolators |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換開關(guān) |
| 應(yīng)用： | 通用型緩沖器/總線擴(kuò)展器 |
| 內(nèi)部開關(guān)： | 是 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-DFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
LTC4303
7
4303fb
OUTPUT SIDE
50pF
0.5V/DIV
INPUT SIDE
150pF
0.5V/DIV
200ns/DIV
4303 F01
INPUT SIDE
50pF
0.5V/DIV
OUTPUT SIDE
150pF
0.5V/DIV
20ns/DIV
4303 F02
OPERATIO
Figure 1. Input-Output Connection t
PLH
the two sides. This effect is displayed in Figure 1 for a
V
CC
= 3.3V and a 10k pull-up resistor on each side (50pF
on one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective t
PLH
is negative.
There is a propagation delay, t
PHL
, through the connec-
tion circuitry for falling waveforms. Figure 2 shows the
falling edge waveforms. An external driver pulls down
the voltage on the side with 50pF capacitance; LTC4303
pulls down the voltage on the opposite side with a delay
of 80ns. This delay is always positive and is a function of
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
Typical Performance Characteristics section shows t
PHL
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent capacitance on both sides
of the part. Larger output capacitances translate to longer
delays. Users must quantify the difference in propagation
times for a rising edge versus a falling edge in their systems
and adjust setup and hold times accordingly.
READY Digital Output
The READY pin provides a digital ag which indicates the
status of the connection circuitry described previously in
the Connection Circuitry section. READY is high when
the connection circuitry is active, and pulls low when
there is not a valid connection. The pin is driven by an
open drain pull-down capable of sinking 3mA while hold-
ing 0.4V on the pin. Connect a resistor of 10k to V
CC
to
provide the pull-up.
ENABLE
When the ENABLE pin is driven below 0.8V with respect
to the LTC4303s ground, the backplane side is discon-
nected from the card side, and the READY pin is internally
pulled low. When the pin is driven above 2V, the part waits
for data transactions on the IN side to be complete and
for the OUT side to be high (as described in the Start-Up
section) before connecting the two sides. At this time the
internal pull-down on READY releases. When ENABLE is
low, automatic clocking is disabled.
A rising edge on ENABLE after a stuck bus condition has
occurred forces a connection between SDAIN, SDAOUT
and SCLIN, SCLOUT even if bus idle conditions are not
met. At this time the internal 30ms timer is reset but not
disabled.
Rise Time Accelerators
Once connection has been established, rise time accelerator
circuits on all four SDA and SCL pins are activated. These
allow the use of larger pull-up resistors, reducing power
consumption, or bus capacitance beyond that speci ed
in I
2
C, while still meeting system rise time requirements.
During positive bus transitions, the LTC4303 switches in
3.5mA (typical) of current to quickly slew the SDA and
SCL lines once their DC voltages exceed 0.8V. Choose a
pull-up resistor so that the bus will rise on its own at a
rate of at least 0.8V/祍 to guarantee activation of the ac-
celerators. Rise time accelerators turn off when SDA and
SCL lines are approximately 1V below V
CC
.The rise time
accelerators are automatically disabled during automatic
clocking.
Figure 2. Input-Output Connection t
PHL
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