參數(shù)資料
型號(hào)： LTC4278CDKD#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 7/42頁(yè)
文件大?。?/td> 0K
描述： IC PD IEEE 802.3AT 25.5W 32-DFN
標(biāo)準(zhǔn)包裝： 2,500
控制器類型： 供電設(shè)備接口控制器（PD）
接口： IEEE 802.3af
電源電壓： 4.5 V ~ 20 V
電流 - 電源： 6.4mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-DFN（7x4）裸露焊盤(pán)
包裝： 帶卷 (TR)
LTC4278
15
4278fc
APPLICATIONS INFORMATION
SIGNATURE CORRUPT OPTION
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE. The LTC4278 signature resistance can be corrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalid signature per the IEEE 802.3af/IEEE 802.3at speci-
fication, and alerts the PSE not to apply power. Invoking
the SHDN pin also ceases operation for classification and
disconnects the LTC4278 load from the PD input. If this
feature is not used, connect SHDN to VPORTN.
Table 2. Summary of Power Classifications and LTC4278
RCLASS Resistor Selection
CLASS
USAGE
MAXIMUM
POWER LEVELS
AT INPUT OF PD
(W)
NOMINAL
CLASSIFICATION
LOAD CURRENT
(mA)
LTC4278
RCLASS
RESISTOR
(Ω, 1%)
0
Type 1
0.44 to 12.95
< 0.4
Open
1
Type 1
0.44 to 3.84
10.5
124
2
Type 1
3.84 to 6.49
18.5
69.8
3
Type 1
6.49 to 12.95
28
45.3
4
Type 2
12.95 to 25.5
40
30.9
2-EVENT CLASSIFICATION AND THE T2P PIN
A Type 2 PSE may declare the availability of high power by
performing a 2-event classification (layer 1) or by com-
municating over the high speed data line (layer 2). A Type
2 PD must recognize both layers of communication. Since
layer 2 communication takes place directly between the
PSE and the LTC4278 load, the LTC4278 concerns itself
only with recognizing 2-event classification.
In 2-event classification, a Type 2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
when the PSE presents an input voltage between 15.5V
to 20.5V and the LTC4278 presents a class 4 load cur-
rent. The PSE then drops the input voltage into the mark
voltage range of 7V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
The PSE repeats this sequence, signaling the 2nd Clas-
sification and 2nd mark event occurrence. This alerts the
LTC4278 that a Type 2 PSE is present. The Type 2 PSE
then applies power to the PD and the LTC4278 charges
up the reservoir capacitor C1 with a controlled inrush cur-
rent. When C1 is fully charged, and the LTC4278 declares
power good, the T2P pin presents an active low signal, or
low impedance output with respect to VPORTN. The T2P
output becomes inactive when the LTC4278 input voltage
falls below undervoltage lockout threshold.
Figure 3. 25k Signature Resistor with Disable
VPORTP
VPORTN
SHDN
LTC4278
SIGNATURE DISABLE
4278 F03
25k SIGNATURE
RESISTOR
16k
TO
PSE
CLASSIFICATION
Classification provides a method for more efficient power
allocation by allowing the PSE to identify a PD power clas-
sification. Class 0 is included in the IEEE specification for
PDs that do not support classification. Class 1-3 partitions
PDs into three distinct power ranges. Class 4 includes the
new power range under IEEE802.3at (see Table 2).
During classification probing, the PSE presents a fixed
voltage between 15.5V and 20.5V to the PD (Figure 1).
The LTC4278 asserts a load current representing the PD
power classification. The classification load current is
programmed with a resistor RCLASS that is chosen from
Table 2.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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