參數(shù)資料
型號(hào)： LTC4261IGN-2#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 26/34頁(yè)
文件大?。?/td> 361K
描述： IC CTRLR HOTSWAP W/ADC 28-SSOP
標(biāo)準(zhǔn)包裝： 49
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開關(guān)： 無(wú)
電源電壓： 9 V ~ 11.2 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
LTC4261/LTC4261-2
26
42612fc
Alert Response Protocol
The LTC4261/LTC4261-2 implement the SMBus Alert
Response Protocol as shown in Figure 15. If enabled
to do so through the ALERT register C, the LTC4261/
LTC4261-2 will respond to faults by pulling the ALERT
pin low. Multiple LTC4261/LTC4261-2s can share a com-
mon ALERT line and the protocol allows a master to de-
termine which LTC4261/LTC4261-2s are pulling the line
low. The master begins by sending a START bit followed
by the special Alert Response Address (0001 100)b with
the R/W bit set to one. Any LTC4261/LTC4261-2 that is
pulling its ALERT pin low will acknowledge and begin
sending back its individual slave address.
Figure 15. LTC4261 Serial Bus SDA Alert Response Protocol
APPLICATIONS INFORMATION
Single-Wire Broadcast Mode
The LTC4261/LTC4261-2 provides a single-wire broadcast
mode in which selected register data are sent out to the
SDAO pin without clocking the SCL line (Figure 16). The
single-wire broadcast mode is enabled by setting the
ADR1 pin high and the ADR0 pin low (the I
2
C interface is
disabled). At the end of each conversion of the three ADC
channels, a stream of eighteen bits are broadcasted to
SDAO with a serial data rate of 15.3kHz ?0% in a format
as illustrated in Figure 17. The data bits are encoded with
an internal clock in a way similar to Manchester encoding
that can be easily decoded by a microcontroller or FPGA.
Each data bit consists of a noninverting phase and an
inverting phase. During the conversion of each ADC chan-
nel, SDAO is idle at high. At the end of the conversion, the
SDAO pulls low. The START bit indicates the beginning of
data broadcasting and is used along with the dummy bit
(DMY) to measure the internal clock cycle (i.e., the serial
data rate). Following the DMY bit are two channel code
bits CH1 and CH0 labeling the ADC channel (see Table
10). Ten data bits of the ADC channel (ADC9-0) and three
FAULT register bits (B2, B1 and B0) are then sent out. A
parity bit (PRTY) ends each data stream. After that the
SDAO line enters the idle mode with SDAO pulled high.
The following data reception procedure is recommended:
0. Wait for INTV
CC
 rising edge.
1. Wait for SDAO falling edge.
2. The first falling edge could be a glitch, so check again
after a delay of 10祍. If back to high, wait again. If still
low, it is the START bit.
3. Use the following low-to-high and high-to-low transis-
tions to measure 1/2 of the internal clock cycle.
An arbitration scheme ensures that the LTC4261/
LTC4261-2 with the lowest address will have priority;
all others will abort their response. The successful re-
sponder will then release its ALERT pin while any others
will continue to hold their ALERT pins low. Polling may
also be used to search for any LTC4261/LTC4261-2 that
have detected faults. Any LTC4261/LTC4261-2 pulling its
ALERT pin low will also release it if it is individually ad-
dressed during a read or write transaction.
The ALERT signal will not be pulled low again until the
FAULT register indicates a different fault has occurred or
the original fault is cleared and it occurs again. Note that
this means repeated or continuing faults will not gener-
ate alerts until the associated FAULT register bit has been
cleared.
S
ALERT
RESPONSE
ADDRESS
0 0 0 1 1 0 0
DEVICE
ADDRESS
0 0 1 a3:a0 0  1
1
R
0
42612 F15
A
A
P
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LTC4261IUFD#TR 功能描述:IC CTRLR HOTSWAP W/ADC 24-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:119 系列:- 類型:熱交換控制器 應(yīng)用:通用型，PCI Express? 內(nèi)部開關(guān):無(wú) 電流限制:- 電源電壓:3.3V，12V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-TQFP 供應(yīng)商設(shè)備封裝:80-TQFP（12x12） 包裝:托盤 產(chǎn)品目錄頁(yè)面:1423 (CN2011-ZH PDF)
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