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參數(shù)資料
| 型號： | LTC4261IGN-2#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 21/34頁 |
| 文件大?。?/td> | 361K |
| 描述： | IC CTRLR HOTSWAP W/ADC 28-SSOP |
| 標準包裝： | 49 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內(nèi)部開關： | 無 |
| 電源電壓： | 9 V ~ 11.2 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
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LTC4261/LTC4261-2
21
42612fc
the lower address wins arbitration and responds first. The
ALERT line will also be released if the device is addressed
by the bus master.
Once the ALERT signal has been released for one fault,
it will not be pulled low again until the FAULT register
indicates a different fault has occurred, or the original
fault is cleared and it occurs again. Note that this means
repeated or continuing faults will not generate alerts until
the associated FAULT register bit has been cleared.
Resetting Faults
Faults are reset with any of the following conditions.
First, writing zeros to the FAULT register B will clear the
associated fault bits. Second, the entire FAULT register
is cleared when either the ON pin or bit D3 goes from
high to low, or if INTV
CC
falls below its 4.25V undervolt-
age lockout. Pulling the UVL pin below its 1.21V reset
threshold also clears the entire FAULT register. When the
UVL pin is brought back above 1.21V but below 2.291V,
the undervoltage fault bit B1 is set if the UVH pin is below
2.56V. This can be avoided by holding the UVH pin above
2.56V while toggling the UVL pin to reset faults. Finally,
when EN is brought from high to low, all fault bits except
bit B4 are cleared. The bit B4 that indicates an EN change
of state will be set.
Fault bits with associated conditions that are still pres-
ent (as indicated in the STATUS Register A) cannot be
cleared. The FAULT register will not be cleared when
auto-retrying. When auto-retry is disabled, the existence
of B0 (overvoltage), B1 (undervoltage), B2 (overcurrent)
or B3 (power bad) fault keeps the FET off. After the fault
bit is cleared and a delay of t
D
(for B0, B1 and B3) or 4t
D
(for B4) expires, the FET will turn on again. Note that if
the overvoltage fault bit B0 is cleared by writing a zero
through I
2
C, the FET is allowed to turn on without a de-
lay. If auto-retry is enabled, then a high value in A0, A1,
A2 or A3 will hold the FET off and the FAULT register is
ignored. Subsequently, when the A0, A1, A2 and A3 bits
are cleared, the FET is allowed to turn on again.
Turning the LTC4261/LTC4261-2 On and Off
Many methods of on/off control are possible using the
ON, EN, UV/OV, FLTIN or PGIO pins along with the I
2
C
port. The EN pin works well with logic inputs or float-
ing switch contacts; I
2
C control is intended for systems
where the board operates only under command of a cen-
tral control processor and the ON pin is useful with sig-
nals referenced to RTN, as are the UV (UVH, UVL) and
OV pins. PGIO and FLTIN control nothing directly, but are
useful for I
2
C monitoring of connection sense or other
important signals.
On/off control is possible with or without I
2
C interven-
tion. Further, the LTC4261/LTC4261-2 may reside on
either the removable board or on the backplane. Even
when operating autonomously, the I
2
C port can still ex-
ercise control over the GATE output, although depending
on how they are connected, EN and ON could subse-
quently override conditions set by I
2
C. UV, OV and other
fault conditions seize control as needed to turn off the
GATE output, regardless of the state of EN, ON or the I
2
C
port. Figure 8 shows five configurations of on/off control
of the LTC4261/LTC4261-2.
Determining factors in selecting a pin configuration for
autonomous operation are the polarity and voltage of the
controlling signal.
Optical Isolation. Figure 9a shows an opto-isolator driv-
ing the ON pin. Rising and falling edges at the ON pin
turn the GATE output on and off. If ON is already high
when power is applied, GATE is delayed one t
D
period.
The status of ON can be examined or overridden through
the I
2
C port at register bit D3. This circuit works in both
backplane and board resident applications.
Logic Control. Figure 9b shows an application using log-
ic signal control. Again, the ON pin is used as an input;
all remarks made concerning opto-isolator control apply
here as well.
APPLICATIONS INFORMATION
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