參數(shù)資料
型號(hào)： LTC4261IGN-2#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 23/34頁(yè)
文件大?。?/td> 361K
描述： IC CTRLR HOTSWAP W/ADC 28-SSOP
標(biāo)準(zhǔn)包裝： 49
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 9 V ~ 11.2 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
LTC4261/LTC4261-2
23
42612fc
Configuring the PGIO Pin
Table 6 describes the possible states of the PGIO pin us-
ing the CONTROL register bits D6 and D7. At power-up
the default state is for the PGIO pin to pull low when
the second power good signal is ready. Other uses for
the PGIO pin are to go high impedence when the sec-
ond power good is ready, a general purpose output and a
general purpose input. When the PGIO pin is configured
as a general purpose output, the status of bit C6 is sent
out to the pin. When it is configured as a general pur-
pose input, if the input voltage at PGIO is higher than
1.25V, both bit A6 in the STATUS register and bit B6 in
the FAULT register are set. If the input voltage at PGIO
subsequently drops below 1.25V, bit A6 is cleared. Bit
B6 can be cleared by resetting the FAULT register as de-
scribed previously.
Design Example
As a design example, consider the 200W application with
C
L
 = 330礔 as shown in Figure 1. The operating voltage
range is from 43V to 71V with a UV turn-off threshold of
38.5V.
The design flow starts with calculating the maximum in-
put current:
 
I
MAX
=
200W
36V
= 5.6A
 
where 36V is the minimum input voltage.
The selection of the sense resistor, R
S
, is determined by
the minimum current limit threshold and maximum input
current:
 
R
S
=
DV
SENSE(MIN)
I
MAX
=
45mV
5.6A
= 8mW
The inrush current is set to 0.66A using C
R
:
 
C
R
= C
L
I
RAMP
I
INRUSH
= 330礔
20礎(chǔ)
0.66A
= 10nF
The value of R
F
 and C
F
 are chosen to 1k and 33nF as
discussed previously.
The FET is selected to handle the maximum power dissi-
pation during start-up or an input step. The latter usually
results in a larger power due to summation of the inrush
current charging C
L
 and the load current. For a 36V input
step, the total P
2
t in the FET is approximated by:
 
P
2
t =  36V  I
MAX
(
)
2
t
3
where t is the time it takes to charge up C
L
:
 
t =
C
L
36V
I
INRUSH
=
330礔  36V
0.66A
= 18ms
 
which gives a P
2
t value of 244W
2
s.
Now the P
2
t given by the SOA (safe operating area)
curves of candidate FETs must be higher than 244W
2
s.
The SOA curves of the IRF1310NS provide for 5A at 50V
(250W) for 10ms, which gives a P
2
t value of 625W
2
s and
satisfies the requirement.
Sizing R1, R2 and R3 for the required UV and OV thresh-
old voltages:
V
UV(RISING)
  = 43V, V
UV(FALLING)
  = 38.5V, (using
V
UVH(TH)
 = 2.56V and V
UVH(TH)
 = 2.291V)
V
OV(RISING)
  = 72.3V, V
OV(FALLING)
  = 70.7V (using
V
OV(TH)
 = 1.77V rising and 1.7325V falling)
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz cop-
per foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider is
recommended. Note that 1oz copper exhibits a sheet re-
sistance of about 530礧/square. Small resistances add
up quickly in high current applications. To improve noise
immunity, put the resistive divider to the UV and OV pins
close to the chip and keep traces to V
IN
 and V
EE
 short.
A 0.1礔 capacitor from the UVH or UVL pin (and OV pin
through resistor R2) to V
EE
 helps reject supply noise.
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