參數(shù)資料
型號(hào)： LTC4240IGN#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 20/28頁(yè)
文件大?。?/td> 493K
描述： IC CTRLR HOTSWAP CPCI I2C 28SSOP
標(biāo)準(zhǔn)包裝： 2,500
類型： 熱交換控制器
應(yīng)用： CompactPCI?
內(nèi)部開關(guān)： 無
電源電壓： 3.3V，5V，±12V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
LTC4240
20
4240f
On Resistance
The CompactPCI specification limits the total IR drop of
the FET plus the IR drop of the sense resistor to 100mV.
For a nominal sense resistor of 0.005&, if the user limits
the 3.3V supply load current to 8.7A, then the maximum
FET resistance should be less than 0.0063&. Similarly, for
a 6.2A load current on the 5V supply and a 0.007& sense
resistor, the maximum 5V FET resistance should be
0.0088&. Note that above values of FET resistance are
worst case over temperature (on the FETs datasheet, find
the resistance vs temperature curve and de-rate the room
temperature maximum value).
Breakdown Voltage
The maximum DC voltage that can appear across the
drain/source of the external power FET is 5V +10%. During
transient events and hot swap conditions, parasitic induc-
tances could cause ringing up to 3 times the supply
voltage. The use of voltage transient suppressors at the 5V
and 3.3V inputs can limit these voltage swings to less than
10V (see front page schematic). Similarly, the largest DC
voltage that is likely to appear across the gate is 12V
+10%. Voltage suppressors on the 12V
IN
 node will also
limit the transient spikes on that node. Additionally, the
total capacitance on the GATE node will serve to filter fast
voltage noise spikes. FETs with a minimum rating of ?0V
on both the drain/source and the gate/source are recom-
mended.
Steady State Power Dissipation
For a user selected maximum load current of 8.7A on the
3.3V power supply and a 0.0063& maximum FET resis-
tance, the DC power dissipation is:
(I
MAX
)
2
(R
DSON,MAX
) = (8.7)(8.7)(0.0063) = 0.477W
This is within the SOA limits of most power FETs.
sense resistor drops to 0.0049& and the largest value of
threshold voltage increases to 60mV. This results in a trip
current of 12.2A.

+
+

5V
IN
5V
IN
R
SENSE
5V
SENSE
V
CB
V
CB(MAX)
= 60mV
V
CB(NOM)
= 55mV
V
CB(MIN)
= 50mV
21
20
I
LOAD(MAX)
LTC4240*
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
4240 F09
Figure 9. Circuit Breaker Equivalent
Circuit for Calculating R
SENSE
APPLICATIO  S I FOR  ATIO
U
U
U
Plug-in board designers are thus limited to using less than
9.8A when a nominal 0.005& resistor is used. Using more
than 9.8A runs the risk of turning off the external FET.
Since the CompactPCI specification allows a maximum
1A/pin, at least 10 pins must be used to supply 9.8A. This
implies that only the 3.3V supply can use a 0.005&
resistor, since the 5V supply has a maximum of 8 pins
available. To adhere to the 1A/pin specification, the 5V
sense resistor should be larger than the 3.3V sense
resistor. Typical applications show a nominal 0.007&
resistor, which results in a 7.04A maximum deliverable
current to the plug-in board loads. The 7.04A current
implies at least 7 pins on the 5V connector. Note that the
thermal considerations of the external FET will also place
limitations on the maximum allowable current.
5V and 3.3V External FET Selection
The LTC4240 uses external power FETs to limit and
modulate the current delivered by the 3.3V and 5V sup-
plies. There are several parameters to consider when
selecting the FET:
1. On resistance.
2. Gate and drain breakdown voltage.
3. Steady state and transient power dissipation.
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