參數(shù)資料
型號(hào): LTC4240IGN#TRPBF
廠商: Linear Technology
文件頁數(shù): 15/28頁
文件大?。?/td> 493K
描述: IC CTRLR HOTSWAP CPCI I2C 28SSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: CompactPCI?
內(nèi)部開關(guān):
電源電壓: 3.3V,5V,±12V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
LTC4240
15
4240f
Table 3 shows the definition for each data bit. PWRGD,
FAULT, RESETIN, and RESETOUT external pins can be
monitored. PRSNT1# and PRSNT2# are PCI signals that
provide information on the power requirements of the
board. Refer to PCI local bus specifications for a detailed
description. FAULTCODE1 and FAULTCODE0 are two in-
ternal binary encoded signals that, along with FAULT,
indicate which of the four supplies generated a fault. Note
that the FAULTCODE signals are valid only when FAULT
has been asserted low. See Table 4 for description.
Status LED
The main function of the LED is to alert the user when it is
permissible to physically extract the board. The LED
output of the LTC4240 is an open drain N-channel device
capable of sinking 10mA from an externally connected
LED.   This   LED   lights   up   when   RESETOUT
(LOCAL_PCI_RST#) is asserted. Upon application of Early
Power, the long 5V pins will power up the LTC4240 and
light up the Status LED. It will remain on until PWRGD
(HEALTHY#) is asserted and RESETIN (PCI_RST#) is de-
asserted, and the board enters normal operation. Note that
this LED can also be turned on via the I
2
C 2-wire interface.
CPCI Connection Pin Sequence
The staggered length of the CPCI male connector pins
ensures that all power supplies are physically connected
APPLICATIO S I FOR ATIO
U
U
U
Table 3. STATUS Byte Definitions
S7
Logic state of the PRSNT2# pin
S6
Logic state of the PRSNT1# pin
S5
Logic state of the PWRGD pin
S4
Logic state of the RESETOUT pin
S3
Logic state of the RESETIN pin
S2
FAULTCODE1 (see Table 4)
S1
FAULTCODE0 (see Table 4)
S0
Logic state of the FAULT pin
Table 4. FAULTCODE Encoding Description for Receive Byte
FAULTCODE0    FAULTCODE1
FAULT
Supply Causing Fault
LO
LO
LO
3V
IN
LO
HI
LO
5V
IN
HI
LO
LO
12V
IN
HI
HI
LO
V
EEIN
X
X
HI
None
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
STOP
SDA
START
ACK
ACK
R/WR=1
ADDR 4   ADDR 3   ADDR 2   ADDR 1   ADDR 0
S5
S4
S3
S2
S1
S0
0
1
S7
S6
ADDRESS BYTE
DATA BYTE
4240 F03
Figure 3. Receive Byte Protocol
to the LTC4240 before back-end power is allowed to ramp
(BD_SEL# asserted low). The long pins, which include 5V,
3.3V, V(I/O) and GND mate first. The short pins, which
includes BD_SEL# (OFF/ON), mate last. At least one long
5V power pin must be connected to the LTC4240 in order
for the PRECHARGE voltage to be available during Early
Power. The external components connected to the
precharge pin require long 3.3V.
The following is a typical hot plug sequence:
1. ESD clips make contact.
2. Long power and ground pins make contact and Early
Power is established (see Early Power section). The 1V
PRECHARGE voltage becomes valid at this stage. Power
is applied to the pull-up resistors connected to FAULT,
PWRGD and OFF/ON pins. The status LED is lit, indicat-
ing that the plug-in board is in the process of being
connected (LOCAL_PCI_RST# is asserted). All power
switches are off.
3. Medium length pins make contact. There are six 5V and
eight 3.3V medium length power pins, bringing the 5V
total to 8 pins and the 3.3V total to 10 pins. The
maximum DC current for the 3.3V and 5V supplies is
10A and 8A, respectively. The I
2
C command latch is
initialized to allow seamless CPCI Hot Swap operation.
The LTC4240 can be used as a Hot Swap controller
without ever establishing I
2
C communication. Both
FAULT and PWRGD continue to be pulled up high at this
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