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參數(shù)資料
| 型號： | LTC3853EUJ#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.15 A DUAL SWITCHING CONTROLLER, 830 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封裝： | 6 X 6 MM, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 1780K |
| 代理商： | LTC3853EUJ#TR |
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LTC3853
12
3853fa
voltage below 0.8V (e.g., SGND). To select pulse skipping
mode of operation, tie the MODE/PLLIN pin to INTVCC. To
select Burst Mode operation, float the MODE/PLLIN pin.
When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifier EA will decrease the voltage on the ITH
pin. When the ITH voltage drops below 0.5V, the internal
sleep signal goes high (enabling “sleep” mode) and both
external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When the controller
is enabled for Burst Mode operation, the inductor current
is not allowed to reverse. The reverse current comparator
(IREV)turnsoffthebottomexternalMOSFETjustbeforethe
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
underlargetransientconditions.Thepeakinductorcurrent
is determined by the voltage on the ITH pin, just as in nor-
mal operation. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continuous
mode has the advantages of lower output ripple and less
interference with audio circuitry.
When the MODE/PLLIN pin is connected to INTVCC, the
LTC3853 operates in PWM pulse skipping mode at light
loads. At very light loads, the current comparator, ICMP,
mayremaintrippedforseveralcyclesandforcetheexternal
top MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage. The switching frequency
of the LTC3853’s controllers can be selected using the
FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ/PLLFLTR
pin can be used to program the controller’s operating
frequency from 250kHz to 750kHz.
A phase-locked loop (PLL) is available on the LTC3853
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized. A series R-C should be connected
between the FREQ/PLLFLTR pin and SGND to serve as
the PLL’s loop filter.
Power Good (PGOOD12 and PGOOD3 Pins)
The PGOOD12 pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD12 pin low when either VFB1 or VFB2 pin
voltage is not within ±7.5% of the 0.8V reference voltage.
The PGOOD12 pin is also pulled low when either RUN1
or RUN2 pin is below 1.2V or when the LTC3853 is in the
soft-start or tracking phase. When the VFB pin voltage
is within the ±7.5% requirement, the MOSFET is turned
off and the pin is allowed to be pulled up by an external
resistor to a source of up to 6V. The PGOOD12 pin will
flag power good immediately when both VFB1 and VFB2
pins are within the ±7.5% window. However, there is an
internal 17s power bad mask when either VFB is out of
the ±7.5% window. PGOOD3 monitors VFB3 and is also
pulled low when RUN3 is below 1.2V.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (> 7.5%) as well as other more serious con-
ditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
OPERATION
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