參數(shù)資料
型號(hào)： LTC3776EGN
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： Dual 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination
中文描述： 1 A DUAL SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO24
封裝： 0.150 INCH, PLASTIC, SSOP-24
文件頁(yè)數(shù)： 19/28頁(yè)
文件大?。?/td> 429K
代理商： LTC3776EGN
19
LTC3776
3776f
frequency, when there is a clock signal applied to SYNC/
SSEN, is shown in Figure 9 and specified in the Electrical
Characteristics table. Note that the LTC3776 can only be
synchronized to an external clock whose frequency is
within range of the LTC3776’s internal VCO, which is
nominally 200kHz to 1MHz. This is guaranteed, over
temperature and process variations, to be between 250kHz
and 850kHz. A simplified block diagram is shown in
Figure 10.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
OSC
, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f
OSC
, current is sunk continuously, pulling down the
PLLLPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
APPLICATIU
W
U
U
PLLLPF PIN VOLTAGE (V)
0
0
F
0.5
1
1.5
2
3776 F09
2.4
200
400
600
800
1000
1200
1400
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
R
LP
C
LP
3776 F10
PLLLPF
EXTERNAL
OSCILLATOR
SYNC/
SSEN
Figure 10. Phase-Locked Loop Block Diagram
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor C
LP
holds the voltage.
The loop filter components, C
LP
and R
LP
, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01
μ
F.
Typically, the external clock (on SYNC/SSEN pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
0V
Floating
V
IN
RC Loop Filter
Capacitor to
GND
SYNC/SSEN PIN
GND
GND
GND
Clock Signal
V
IN
FREQUENCY
300kHz
550kHz
750kHz
Phase-Locked to External Clock
Spread Spectrum Operation
450kHz to 550kHz
Low Supply Operation
Although the LTC3776 can function down to below 2.4V,
the maximum allowable output current is reduced as V
IN
decreases below 3V. Figure 11 shows the amount of
change as the supply is reduced down to 2.4V. Also shown
is the effect on V
REF
.
INPUT VOLTAGE (V)
75
N
85
95
105
80
90
100
2.2
2.4
2.6
2.8
3776 F11
3.0
2.1
2.0
2.3
2.5
2.7
2.9
V
REF
MAXIMUM
SENSE VOLTAGE
Figure 11. Line Regulation of V
REF
and
Maximum Sense Voltage for Low Input Supply
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC3776EGN#PBF 功能描述:IC CTLR SYNC DUAL 24-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:控制器，DSP 輸入電壓:4.5 V ~ 25 V 輸出數(shù):2 輸出電壓:最低可調(diào)至 1.2V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:30-TFSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:30-TSSOP 包裝:帶卷 (TR)
LTC3776EGN#TRPBF 功能描述:IC CNTRLR SYNC DUAL 24-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:43 系列:- 應(yīng)用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-QFN（7x7） 包裝:管件
LTC3776EGNPBF 制造商:Linear Technology 功能描述:DC-DC Controller Dual Step-Down SSOP24
LTC3776EUF 制造商:Linear Technology 功能描述:DC DC Cntrlr Dual-OUT Sync Step Down 2.75V to 9.8V Input 24-Pin QFN EP
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