參數(shù)資料
型號(hào): LTC3776EGN
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: Dual 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination
中文描述: 1 A DUAL SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO24
封裝: 0.150 INCH, PLASTIC, SSOP-24
文件頁(yè)數(shù): 10/28頁(yè)
文件大?。?/td> 429K
代理商: LTC3776EGN
10
LTC3776
3776f
OPERATIOU
When the load current increases, it causes a slight
decrease in V
FB
relative to the reference, which in turn
causes the I
TH
voltage to increase until the average induc-
tor current matches the new load current. While the top
P-channel MOSFET is off, the bottom N-channel MOSFET
is turned on until the beginning of the next cycle.
Short-Circuit Protection
When an output is shorted to ground, the switching
frequency of that controller is reduced to 1/5 of the normal
operating frequency.
The short-circuit threshold on V
FB2
is based on the smaller
of 0.12V and a fraction of the voltage on the V
REF
pin. This
also allows V
OUT2
to start up and track V
OUT1
more easily.
Note that if V
OUT1
is truly short-circuited (V
OUT1
= V
FB1
=
0V), then the LTC3776 will try to regulate V
OUT2
to 0V if
V
OUT1
is connected to the V
REF
pin.
Output Overvoltage Protection
As further protection, the overvoltage comparator (OV)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the V
FB
pin has risen 13.33%
above its resolution point, the external P-channel MOSFET
is turned off and the N-channel MOSFET is turned on until
the overvoltage is cleared.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/SSEN Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
The switching frequency of the LTC3776’s controllers can
be selected using the PLLLPF pin.
If the SYNC/SSEN pin is tied to ground, the PLLLPF pin can be
floated, tied to V
IN
, or tied to SGND to select 550kHz, 750kHz,
or 300kHz constant frequency operation, respectively.
A phase-locked loop (PLL) is available on the LTC3776 to
synchronize the internal oscillator to an external clock
source that connected to the SYNC/SSEN pin. In this case,
a series RC should be connected between the PLLLPF pin
and SGND to serve as the PLL’s loop filter. The LTC3776
(Refer to Functional Diagram)
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
The LTC3776 is shut down by pulling the RUN/SS pin low.
In shutdown, all controller functions are disabled and the
chip draws only 9
μ
A. The TG outputs are held high (off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7
μ
A current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3776’s two controllers are enabled.
The start-up of V
OUT1
is controlled by the LTC3776’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal V
FB1
to the internal
soft-start ramp (instead of the 0.6V reference), which rises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor C
SS
between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
rise linearly from approximately 0.65V to 1.25V (being
charged by the internal 0.7
μ
A current source), the EAMP
regulates the V
FB1
proportionally linearly from 0V to 0.6V.
The start-up of V
OUT2
is controlled by the voltage on the
V
REF
pin. Typically, V
OUT1
is connected to the V
REF
pin to
allow the start-up of V
OUT2
to “track” that of 1/2 V
OUT1
.
Note that if either V
OUT1
or V
OUT2
is less than 90% (lower
PGOOD threshold) of its regulation point (in either a
startup or short-circuit condition), then channel one’s
inductor current is not allowed to reverse (i.e., discontinu-
ous operation is forced). This is to prevent a minimum on-
time condition during startup.
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