參數(shù)資料
型號: LTC3776EGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: Dual 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination
中文描述: 1 A DUAL SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO24
封裝: 0.150 INCH, PLASTIC, SSOP-24
文件頁數(shù): 18/28頁
文件大?。?/td> 429K
代理商: LTC3776EGN
18
LTC3776
3776f
During soft-start, the start-up of V
OUT1
is controlled by
slowly ramping the positive reference to the error amplifier
from 0V to 0.6V, allowing V
OUT1
to rise smoothly from 0V
to its final value. The default internal soft-start time is 1ms.
This can be increased by placing a capacitor between the
RUN/SS pin and SGND. In this case, the soft-start time will
be approximately:
t
C
mV
A
μ
SS
SS
1
600
0 7
.
=
V
REF
Pin
The regulation of V
OUT2
is controlled by the voltage on the
V
REF
pin. Normally this pin is used in DDR memory
termination applications so that V
OUT2
tracks 1/2 V
OUT1
as
shown in Figure 8.
APPLICATIU
Channel 2’s output voltage is set to 1/2 V
REF
by connecting
the V
FB2
pin to V
OUT2
. To improve the frequency response,
a feed-forward capacitor, C
FF
, may be used. Great care
should be taken to route the V
FB
line away from noise
sources, such as the inductor or the SW line.
W
U
U
3.3V OR 5V
RUN/SS
RUN/SS
C
SS
C
SS
D1
3776 F07
Figure 7. RUN/SS Pin Interfacing
LTC3776
V
FB2
V
FB1
V
OUT1
V
OUT2
R
B
C
FF
R
A
3776 F06
Figure 6. Setting Output Voltage
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3776.
Pulling the RUN/SS pin below 0.65V puts the LTC3776 into
a low quiescent current shutdown mode (I
Q
= 9
μ
A). If
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3776 comes out of shutdown and
is given by:
t
V
C
.
A
s F C
/
DELAY
SS
μ
SS
=
=
0 65
.
0 7
0 93
.
This pin can be driven directly from logic as shown in
Figure 7. Diode D1 in Figure 7 reduces the start delay but
allows C
SS
to ramp up slowly providing the soft-start
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
LTC3776
V
FB2
V
OUT2
V
OUT1
V
FB1
V
REF
3776 F08
R1B
R1A
Figure 8. Using the V
REF
Pin (V
OUT2
is Regulated to 1/2 V
REF
= 1/2V
OUT1
)
Phase-Locked Loop and Frequency Synchronization
The LTC3776 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the external
P-channel MOSFET of controller 1 to be locked to the
rising edge of an external clock signal applied to the
SYNC/SSEN pin. The turn-on of controller 2’s external
P-channel MOSFET is thus 180 degrees out of phase with
the external clock. The phase detector is an edge sensitive
digital type that provides zero degrees phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics of
the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
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