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參數(shù)資料
| 型號(hào)： | LTC3766IGN#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 316 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 5/60頁 |
| 文件大?。?/td> | 607K |
| 代理商： | LTC3766IGN#TRPBF |
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LTC3766
13
3766f
OPERATION
The LTC3766 will begin a soft-start sequence when the
RUN pin is high, adequate voltage is present on both the
VIN and VCC pins, and switching is detected on the SW
pin. Note that the LTC3766 must see switching on the SW
pin prior to initiating a soft-start sequence to ensure that
the LTC3765 is ready for control hand-off. The soft-start
sequence begins by first measuring the voltage on the FB
pin and then rapidly pre-setting the soft-start capacitor
voltage to a level that corresponds to the output voltage,
VOUT. This is done to provide a smooth ramp on the output
voltageascontrolistransferredfromprimarytosecondary,
as well as to avoid any unnecessary start-up delay. Once
the soft-start capacitor has been pre-set to the appropriate
level, the LTC3766 then sends a brief sequence of pulses
through the pulse transformer to establish a communica-
tion lock between the LTC3766 and the LTC3765. At this
point, the LTC3766 assumes control of the primary-side
MOSFETs, and the soft-start capacitor begins charging
with a constant current of 5μA, continuing the soft-start
of the main output voltage. Note that the soft-start volt-
age is used to limit the effective level of the reference into
the error amplifier. This technique maintains closed-loop
control of the output voltage during the secondary-side
soft-start interval.
Gate Drive Encoding
Since the LTC3766 controller normally resides on the
secondary side of an isolation barrier, communication to
the primary-side gate driver must be done through a small
pulse transformer. A common scheme for communicating
gate drive (PWM) information makes use of short pulses
and relies on receiver latches to “remember” whether
power MOSFETs should be either on or off. However,
this system is prone to get into the wrong state, and has
difficulty distinguishing a loss of signal from a legitimate
zero duty cycle signal. To alleviate these concerns, the
LTC3766 uses a proprietary gate drive encoding scheme
that reliably maintains constant contact across the isola-
tion barrier without introducing any delay.
The LTC3766 encodes PWM information onto the PT+
and PT– outputs, which are in turn connected to a small
pulsetransformerthroughaDC-blockingcapacitor.These
outputs are driven in a complementary fashion, with a
constant 79% duty cycle. This results in a stable volt-
second balance, so that the signal amplitude transferred
across the pulse transformer is constant. As shown in
Figure2,thebeginningoftheintervalwhen(VPT+-VPT–)is
positive approximately coincides with the turn-on of the
main primary-side MOSFET. Likewise, the beginning of
the interval when (VPT+-VPT–) is negative coincides with
themaximumdutycycle(forcedturn-offofmainprimary-
sideMOSFET).Attheappropriatetimeduringthepositive
interval, the end of the “on” time (PWM going low) is
signaledbybrieflyapplyingazero-voltdifferentialacross
the pulse transformer. In the event that a zero duty-cycle
signal needs to be sent, this is accomplished naturally
by placing the zero-voltage differential at the beginning
of the positive interval. In this manner, any duty cycle
from 0% to the maximum of 79% can be sent across
the pulse transformer without delay. Figure2 illustrates
the operation of this encoding scheme.
On the primary side, the LTC3765 receives the signal from
the pulse transformer through a DC restoring capacitor.
After communication lock has been established between
the two parts, the LTC3765 extracts clock and duty cycle
information from the signal and uses it to control its
gate driver outputs. Note that, except for a tiny pulse,
Figure 2: Gate Drive Encoding Scheme
(MODE = GND or MODE = VCC)
150ns
+VCC
–VCC
1 CLK PER
VPT+ – VPT–
150ns
3766 F02
1 CLK PER
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