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參數(shù)資料
| 型號： | LTC3766IGN#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 316 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 29/60頁 |
| 文件大?。?/td> | 607K |
| 代理商： | LTC3766IGN#TRPBF |
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LTC3766
35
3766f
APPLICATIONS INFORMATION
the delays should initially be selected so that they are
long, while keeping in mind that the FG delay must be less
than the PG delay to prevent potentially damaging PG/SG
cross-conduction. As a first pass, use a 75k resistor from
FGD to ground for a 415ns delay and 60k resistor from
DELAY to ground for a 622ns delay. The SWP and SWB
waveforms should appear as shown in Figure 18.
The ramp rate on SWB and SWP is to a first order inde-
pendent of duty cycle; however, the starting point of the
ramp is a function of the duty cycle. Therefore, the longest
delay time will be at high duty cycle when VIN is at a mini-
mum. For the lowest switching losses over the range of
input voltage, the delays should be chosen based on the
waveforms when VIN is at its minimum operating voltage.
The resistor value from the FGD pin to ground should be
selected first. This should be chosen to give a delay equal
to the time from PT+ rising until SWB ramps down to ap-
proximately 0V. The FGD resistor value can be determined
from the following equation:
RFGD = tFGD –18ns
(
) 1k
5.1ns
Note that if the FG turns on before the SWP and SWB
voltages have naturally fallen to their minimums, they will
be instantly pulled to their minimum by the FG MOSFET
turning on. This can give the appearance that FG is turn-
ing on after SWB has ramped to 0V, although it is actually
premature.TurningonFGprematurelywillslightlydegrade
efficiency due to increased switching loss; however, if the
fall time of SWP and SWB exceed a maximum FGD delay
of 600ns, it is acceptable to have premature FG turn-on
at low input voltage. Generally, the delay will be adequate
at higher VIN to allow a complete ramp down.
In rare cases, the LTC3765 and LTC3766 will be in delay
phase-out mode when operating at minimum VIN voltage.
This will be apparent because the measured delay will be
smallerthantheprogrammeddelayoneitherorbothchips.
This feature allows the LTC3765 and LTC3766 to operate
at duty cycles up to a maximum of 79% by reducing the
programmed delays when they would otherwise limit the
maximum duty cycle. If this mode is evident, increase VIN
until delay phase-out is no longer active, and then set the
FGD delay as described above.
Having set the FGD delay to optimize for low voltage
switching, the PG delay is next chosen to minimize the
dead time between SG turn-off and PG turn-on. The delay
for the primary gate can be determined by taking the de-
lay set tolerance and rise/fall times into account. The FG
delay setting on the LTC3766 and the PG delay setting on
the LTC3765 are both accurate to within 15% for a range
of resistance values. Given this accuracy, a reasonable
choice for the LTC3765 delay time is to set the PG delay
time to 1.22 tFGD.
Be aware that the fall time of SG and the rise time of PG
cannotbeneglected.Forexample,ifSGisdrivingaMOSFET
with high input capacitance, and PG is driving a MOSFET
with low input capacitance, then SG will fall slowly and
PG will rise quickly. This increases the potential for shoot-
through. Moreover, since SG will not turn off until FG turns
on (make before break), the rise time of FG is also a factor.
A final consideration is that the LTC3765 experiences a
delay in PT+ rising due to the pulse transformer. All of these
considerations can be accounted for in the delay resistor
selection by the following equation, in which tD(PT) is the
delay time from PT+ rising to IN+ rising on the LTC3765,
tR(FG) is the rise time of FG to 2V, tF(SG) is the fall time of
VIN
1 – D
~
VOUT
1 – D
~
VIN
SWP NODE
SWB NODE
PT+
0V
tFGD
3766 F18
Figure 18. SWP and SWB Waveforms
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