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參數(shù)資料
| 型號： | LTC3728LZEUH |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A DUAL SWITCHING CONTROLLER, 590 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 5 X 5 MM, PLASTIC, MO-220WHHD, QFN-28 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大小： | 467K |
| 代理商： | LTC3728LZEUH |
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LTC3728LZ
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3728lzf
APPLICATIONS INFORMATION
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal oscillators. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, fH,
is equal to the capture range, ΔfC:
ΔfH = ΔfC = ±0.5 fO (260kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
lter network on the PLLFLTR pin.
If the external frequency (fPLLIN) is greater than the os-
cillator frequency f0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency is
less than f0SC, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLFLTR pin
is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operat-
ing point the phase comparator output is open and the
lter capacitor CLP holds the voltage. The IC’s PLLIN pin
must be driven from a low impedance source such as a
logic gate located close to the pin. When using multiple
ICs for a phase-locked system, the PLLFLTR pin of the
master oscillator should be biased at a voltage that will
guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A DC voltage of 0.7V to 1.7V applied
to the master oscillator’s PLLFLTR pin is recommended
in order to meet this requirement. The resultant operating
frequency can range from 300kHz to 500kHz.
The loop lter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The lter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10kΩ and CLP is 0.01μF
to 0.1μF.
Minimum On-Time Considerations
Minimum on-time tON(MIN)isthesmallesttimedurationthat
each controller is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
t
V
Vf
ON MIN
OUT
IN
()
<
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for each controller is approximately
100ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
150ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a signicant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
on both controllers when the FCB pin drops below 0.8V.
During continuous mode, current ows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the VIN/VOUT
ratio is low, the synchronous switch may not be on for a
sufcient amount of time to transfer power from the output
capacitor to the secondary load. Forced continuous opera-
tion will support secondary windings providing there is
sufcient synchronous switch duty factor. Thus, the FCB
input pin removes the requirement that power must be
drawn from the inductor primary in order to extract power
from the auxiliary windings. With the loop in continuous
mode, the auxiliary outputs may nominally be loaded
without regard to the primary output load.
The secondary output voltage VSECisnormallysetasshown
in Figure 6a by the turns ratio N of the transformer:
VSEC (N + 1) VOUT
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| LTC3728LZEUH#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:PolyPhase® 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
| LTC3728LZEUH#TRPBF | 功能描述:IC REG CTRLR BUCK PWM CM 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:PolyPhase® 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
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