參數(shù)資料
型號: LTC3446IDE#PBF
廠商: Linear Technology
文件頁數(shù): 7/20頁
文件大?。?/td> 283K
描述: IC REG TRPL BCK/LINEAR 14-DFN
標(biāo)準(zhǔn)包裝: 91
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關(guān): 2.25MHz
電壓/電流 - 輸出 1: 可調(diào)至0.8V,1A
電壓/電流 - 輸出 2: 可調(diào)至0.4V,300mA
電壓/電流 - 輸出 3: 可調(diào)至0.4V,300mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 0.9 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 14-DFN-EP(4x3)
包裝: 管件
LTC3446
7
3446ff
pin FuncTions
MODESEL (Pin 1): Chooses Between Burst Mode Operation 
and Pulse-Skipping Operation at Light Loads. Forcing this
pin below 0.3V allows the buck converter to automatically
enter Burst Mode operation at light loads. Forcing this pin
above 1V disallows entering Burst Mode operation; the
buck converter will cycle skip at light loads. Do not leave
this pin floating. This is a MOS gate input.
V
IN
 (Pin 2): Input Supply to the LTC3446. Must be 
closely decoupled to GND with a 10礔 or greater ceramic
capacitor.
I
TH
 (Pin 3): Buck Error Amplifer Output and Servo-Loop 
Compensation Point.
PGOOD (Pin 4): Supply Monitor Output, Open-Drain 
NMOS.
LV
OUT1
 (Pin 5): Output of the First VLDO Regulator.
LV
IN
 (Pin 6): Input Supply to the LTC3446s VLDO Circuits. 
Bypass LV
IN
 to GND with at least a 1礔 low ESR ceramic
capacitor. Typical LTC3446 application circuits will connect
this pin to the output of the buck converter but this is not
required. The VLDO regulators may be used independently
of the buck converter.
LV
OUT2
 (Pin 7): Output of the Second VLDO Regulator.
LV
FB2
 (Pin 9): Feedback Pin for the Second VLDO Regulator. 
An output divider should be connected from LV
OUT2
 to LV
FB2
 
to set the desired LV
OUT2
 regulated output voltage.
LV
FB1
(Pin 10): Feedback Pin for the First VLDO Regulator. 
An output divider should be connected from LV
OUT1
 to LV
FB1
 
to set the desired LV
OUT1
 regulated output voltage.
ENLDO1/ENLDO2 (Pin 11/Pin 8): Enable Pin for the First 
and Second VLDO Regulators, Respectively. Forcing this
pin above 1V enables the corresponding VLDO regulator
and forcing this pin below 0.3V shuts it down. Each VLDO
regulator draws <1礎(chǔ) of supply current in shutdown. Do
not leave this pin floating. This is a MOS gate input.
BUCKFB (Pin 12): Buck Converters Feedback Pin. Receives 
the feedback voltage from an external resistive divider
across the output. External resistance from this pin to
ground should be equal to or less than 50k.
ENBUCK (Pin 13): Enable Pin for the LTC3446s Buck 
Converter Circuit. Forcing this pin above 1V enables the
buck converter and forcing this pin below 0.3V shuts down
the converter. In shutdown, the buck converter draws <1礎(chǔ)
of supply current. Do not leave this pin floating. This is a
MOS gate input.
SW (Pin 14): Switch Node Connection to Inductor. This 
pin connects to the drains of the internal main and syn-
chronous power MOSFET switches.
GND (Exposed Pad, Pin 15): Ground. The Exposed Pad is 
the only ground and must connect to the PCB ground for
electrical contact and rated thermal performance.
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