參數(shù)資料
型號: LTC3446IDE#PBF
廠商: Linear Technology
文件頁數(shù): 15/20頁
文件大小: 283K
描述: IC REG TRPL BCK/LINEAR 14-DFN
標(biāo)準(zhǔn)包裝: 91
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關(guān): 2.25MHz
電壓/電流 - 輸出 1: 可調(diào)至0.8V,1A
電壓/電流 - 輸出 2: 可調(diào)至0.4V,300mA
電壓/電流 - 輸出 3: 可調(diào)至0.4V,300mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 0.9 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 14-DFN-EP(4x3)
包裝: 管件
LTC3446
15
3446ff
applicaTions inForMaTion
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V
IN
 drops toward V
OUT
, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
In some applications, a more severe transient can be caused
by switching in loads with large (>1礔) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C
OUTB
, causing a rapid drop in V
OUT
. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the load
switch driver. A Hot Swap controller is designed specifically
for this purpose and usually incorporates current limiting,
short-circuit protection, and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
 %Efficiency = 100%  (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3446 circuits: 1) LTC3446 V
IN
 current,
2) switching losses, 3) I
2
R losses, 4) other losses.
1) The V
IN
 current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. V
IN
 current results in a small
(<0.1%) loss that increases with V
IN
, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V
IN
 to ground. The resulting dQ/dt is a current
out of V
IN
 that is typically much larger than the DC bias
current. In continuous mode, I
GATECHG
 = f
O
(QT + QB),
where QT and QB are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to V
IN
 and thus their effects
will be more pronounced at higher supply voltages.
3) I
2
R Losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, RL. In
continuous mode, the average output current flowing
through inductor L is chopped between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
DS(ON)
 and the duty cycle (DC) as
follows:
  R
SW
 = (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1  DC)
4) Other hidden losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these system level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
IN
 has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
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