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參數(shù)資料
| 型號： | LTC2488IDE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 14-DFN |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.9 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-DFN-EP（4x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，雙極；2 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1009A-B-ND - BOARD DELTA SIGMA ADC LTC2488 |
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LTC2488
16
2488fa
APPLICATIONS INFORMATION
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 4).
The external serial clock mode is selected during the power-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion re-
sult is held in an internal static shift register. The device
remains in the sleep state until the rst rising edge of SCK
is seen while CS is LOW. The input data is then shifted
in via the SDI pin on each rising edge of SCK (including
the rst rising edge). The channel selection will be used
for the following conversion cycle. If the input channel is
changed during this I/O cycle, the new settings take effect
on the conversion cycle following the data input/output
cycle. The output data is shifted out the SDO pin on each
falling edge of SCK. This enables external circuitry to
latch the output on the rising edge of SCK. EOC can be
latched on the rst rising edge of SCK and the last bit of
the conversion result can be latched on the 24th rising
edge of SCK. On the 24th falling edge of SCK, the device
begins a new conversion and SDO goes HIGH (EOC = 1)
indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Typically, CS remains LOW during the data output/input
Figure 4. External Serial Clock, Single Cycle Operation
VCC
FO
REF+
REF–
CH0
CH1
CH2
CH3
COM
SCK
SDI
CS
SDO
GND
12
1
13
14
8
9
10
11
7
3
4
6
5
2
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
2.7V TO 5.5V
0.1μF
10μF
4-WIRE
SPI INTERFACE
Hi-Z
2488 F04
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
EOC
12
3
4
5
6
7
8
9
19
20
21
22
23
24
1
0
EN
SGL
A2
A1
A0
ODD
DON'T CARE
MSB
SIG
“0”
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
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