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參數(shù)資料
| 型號： | LTC2488IDE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 14-DFN |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.9 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-DFN-EP（4x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1009A-B-ND - BOARD DELTA SIGMA ADC LTC2488 |
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LTC2488
15
2488fa
APPLICATIONS INFORMATION
After power up, the device initiates an internal reset cycle
which sets the input channel to CH0 to CH1 (IN+ = CH0, IN– =
CH1). The rst conversion automatically begins at power
up using this default input channel. Once the conversion is
complete, a new word may be written into the device.
The rst three bits of the input word consist of two pre-
amble bits and one enable bit. These three bits are used
to enable the input channel selection. Valid settings for
these three bits are 000, 100, and 101. Other combinations
should be avoided.
If the rst three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion.
If the rst three bits shifted into the device are 101, then
the next ve bits select the input channel for the next
conversion cycle (see Table 3).
The rst input bit (SGL) following the 101 sequence
determines if the input selection is differential (SGL =
0) or single-ended (SGL = 1). For SGL = 0, two adjacent
channels can be selected to form a differential input. For
SGL = 1, one of four channels is selected as the positive
input. The negative input is COM for all single ended
operations. The remaining four bits (ODD, A2, A1, A0)
determine which channel(s) is/are selected and the polarity
(for a differential input).
SERIAL INTERFACE TIMING MODES
The LTC2488’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several exible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (FO = LOW) or an external oscillator connected
to the FO pin. For each mode, the operating cycle, data
input format, data output format, and performance remain
the same. Refer to Table 4 for a summary.
Table 3 Channel Selection
MUX ADDRESS
CHANNEL SELECTION
SGL
ODD/
SIGN
A2
A1
A0
0
1
2
3
COM
*0
0000
IN+
IN–
00001
IN+
IN–
01000
IN–
IN+
01001
IN–
IN+
10000
IN+
IN–
10001
IN+
IN–
11000
IN+
IN–
11001
IN+
IN–
*Default at power up
Table 4. Serial Interface Timing Modes
CONFIGURATION
SCK
SOURCE
CONVERSION
CYCLE CONTROL
DATA OUTPUT
CONTROL
CONNECTION AND
WAVEFORMS
External SCK, Single Cycle
Conversion
External
CS and SCK
Figures 4, 5
External SCK, 3-Wire I/O
External
SCK
Figure 6
Internal SCK, Single Cycle
Conversion
Internal
CS↓
Figures 7, 8
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal
Continuous
Internal
Figure 9
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