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參數(shù)資料
| 型號： | LTC2488IDE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 14-DFN |
| 標準包裝： | 91 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.9 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-DFN-EP（4x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1009A-B-ND - BOARD DELTA SIGMA ADC LTC2488 |
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LTC2488
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2488fa
PIN FUNCTIONS
FO(Pin1):FrequencyControlPin.Digitalinputthatcontrols
the internal conversion clock rate. When FO is connected to
ground, the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden by
driving the FO pin with an external clock in order to change
the output rate and the digital lter rejection null.
SDI (Pin 2): Serial Data Input. This pin is used to select the
input channel. The serial data input is applied under control
of the serial clock (SCK) during the data output/input opera-
tion. The rst conversion following a new input is valid.
SCK (Pin 3): Bidirectional, Digital I/O, Clock Pin. In Internal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin. In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power up and during the most recent falling edge of CS.
CS(Pin4):ActiveLOWChipSelect.ALOWonthispinenables
thedigitalinput/outputandwakesuptheADC.Followingeach
conversion, the ADC automatically enters the Sleep mode
and remains in this low power state as long as CS is HIGH.
A LOW-to-HIGH transition on CS during the data output
aborts the data transfer and starts a new conversion.
SDO (Pin 5): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedance state. During the conversion and sleep periods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
GND (Pin 6): Ground. Connect this pin to a common ground
plane through a low impedance connection.
COM (Pin 7): The common negative input (IN–) for all
single ended multiplexer congurations. The voltage on
CH0 to CH3 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
(VIN = IN+ – IN–) from –0.5 VREF to 0.5 VREF. Outside
this input range, the converter produces unique over-range
and under-range output codes.
CH0 to CH3 (Pins 8-11): Analog Inputs. May be pro-
grammed for single-ended or differential mode.
VCC (Pin 12): Positive Supply Voltage. Bypass to GND with
a 10μF tantalum capacitor in parallel with a 0.1μF ceramic
capacitor as close to the part as possible.
REF+ (Pin 13), REF– (Pin 14):
Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (VREF = REF+
– REF–) sets the fullscale range for all input channels.
Exposed Pad (Pin 15): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain oating.
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