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參數(shù)資料
| 型號： | LTC2481CDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT I2C 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 121 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC951A-ND - BOARD DELTA SIGMA ADC LTC2481 |
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LTC2481
13
2481fc
APPLICATIONS INFORMATION
The LTC2481 can only be addressed as a slave. Once
addressed, it can receive conguration bits or transmit the
last conversion result. Therefore the serial clock line SCL
is an input only and the data line SDA is bidirectional. The
device supports the Standard-mode and the Fast-mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the denition of timing for Fast/Standard-mode devices
on the I2C-bus.
The START and STOP Conditions
A START condition is generated by transitioning SDA from
HIGH to LOW while SCL is HIGH. The bus is considered to
be busy after the START condition. When the data transfer
is nished, a STOP condition is generated by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is free
again a certain time after the STOP condition. START and
STOP conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START (Sr) conditions are functionally identical to the
START (S).
Data Transferring
After the START condition, the I2C bus is busy and data
transfer is set between a master and a slave. Data is
transferredoverI2Cingroupsofninebits(onebyte)followed
by an acknowledge bit, therefore each group takes nine
SCL cycles. The transmitter releases the SDA line during
the acknowledge clock pulse and the receiver issues an
Acknowledge (ACK) by pulling SDA LOW or leaves SDA
HIGH to indicate a Not Acknowledge (NACK) condition.
Change of data state can only happen while SCL is LOW.
Accessing the Special Features of the LTC2481
The LTC2481 combines a high resolution, low noise
ΔΣ
analog-to-digital converter with an on-chip selectable
temperature sensor, programmable gain, programmable
digital lter and output rate control. These special features
are selected through a single 8-bit serial input word during
the data input/output cycle (see Figure 3).
The LTC2481 powers up in a default mode commonly
used for most measurements. The device will remain in
this mode until a valid write cycle is performed. In this
default mode, the measured input is external, the GAIN is 1,
the digital lter simultaneously rejects 50Hz and 60Hz
line frequency noise, and the speed mode is 1x (offset
automatically, continuously calibrated).
The I2C serial interface grants access to any or all special
functions contained within the LTC2481. In order to change
the mode of operation, a valid write address followed by 8
bits of data are shifted into the device (see Table 1). The rst
3 bits (GS2, GS1, GS0) control the GAIN of the converter
from 1 to 256. The 4th bit is reserved and should be low.
The 5th bit (IM) is used to select the internal temperature
sensor as the conversion input, while the 6th and 7th bits
(FA, FB) combine to determine the line frequency rejection
mode. The 8th bit (SPD) is used to double the output rate
by disabling the offset auto calibration.
Figure 2. Denition of Timing for F/S-Mode Devices on the I2C-Bus
SDA
SCL
SSr
P
S
tf
tLOW
tHD;STA
tBUF
tSP
tSU;STA
tSU;STO
tHD;DAT
tHIGH
tSU;DAT
tr
2481 F02
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